Ali Saidi fe3fbe624e config: Fix issue with changeset: a4739b6f799d.

2013-01-08 17:12:22 -05:00

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Benchmarks.py

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CacheConfig.py

Regression: Use CPU clock and 32-byte width for L1-L2 bus

2012-10-15 08:08:08 -04:00

Caches.py

config: Unify caches used in regressions and adjust L2 MSHRs

2012-10-30 07:44:08 -04:00

cpu2000.py

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FSConfig.py

config: Do not use hardcoded physmem in fs script

2013-01-07 13:05:38 -05:00

O3_ARM_v7a.py

cpu: Rename defer_registration->switched_out

2013-01-07 13:05:45 -05:00

Options.py

config: Fix description of checkpoint option from cycle to tick

2012-11-19 11:21:09 -05:00

Simulation.py

config: Fix issue with changeset: a4739b6f799d.

2013-01-08 17:12:22 -05:00

SysPaths.py

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