Nathan Binkert 5ad139375e isa_parser: move more stuff into the ISAParser class

2010-02-26 18:14:48 -08:00

..

alpha

O3PCU: Split loads and stores that cross cache line boundaries.

2010-02-12 19:53:20 +00:00

arm

O3PCU: Split loads and stores that cross cache line boundaries.

2010-02-12 19:53:20 +00:00

mips

O3PCU: Split loads and stores that cross cache line boundaries.

2010-02-12 19:53:20 +00:00

power

O3PCU: Split loads and stores that cross cache line boundaries.

2010-02-12 19:53:20 +00:00

sparc

O3PCU: Split loads and stores that cross cache line boundaries.

2010-02-12 19:53:20 +00:00

x86

O3PCU: Split loads and stores that cross cache line boundaries.

2010-02-12 19:53:20 +00:00

isa_parser.py

isa_parser: move more stuff into the ISAParser class

2010-02-26 18:14:48 -08:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

Registers: Add a registers.hh file as an ISA switched header.

2009-07-08 23:02:21 -07:00