QQeg 08ed87bc9d arch-riscv: Add template Vector1Vs1VdMaskDeclare ...

This commit adds a new template, Vector1Vs1VdMaskDeclare, to replace
the use of Vector1Vs1RdMaskDeclare in Vector1Vs1VdMaskFormat.

The change addresses the issue with the number of indices in srcRegIdxArr.
Only two indices are available in Vector1Vs1RdMaskDeclare, but instructions
that use Vector1Vs1VdMaskFormat, like 'vmsbf', require three indices
(for vs1, vs2(old_vd), and vm) to function correctly.

Change-Id: I0c966e11289ce07efcc3b0cc56948311289530ad

2024-01-28 09:38:11 +00:00

..

arch

arch-riscv: Add template Vector1Vs1VdMaskDeclare

2024-01-28 09:38:11 +00:00

base

base: Add a check for edge case

2024-01-23 11:35:54 -08:00

cpu

misc: Remove all references to GCN3

2024-01-17 11:11:06 -06:00

dev

dev-amdgpu: Limit SDMA NOP count to wptr boundary (#806)

2024-01-25 15:35:35 -08:00

doc

…

doxygen

…

gpu-compute

misc: Remove all references to GCN3

2024-01-17 11:11:06 -06:00

kern

misc: Fix 'maybe-uninitialized' warn turn off (#706)

2023-12-21 18:45:56 -08:00

learning_gem5

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

mem

arch-gcn3: Remove gcn3 (#781)

2024-01-25 10:14:46 -08:00

proto

scons: Use Kconfig to configure gem5.

2023-11-23 08:26:10 +08:00

python

arch-riscv: fix riscv matched board for se mode (#677)

2023-12-14 00:05:02 -08:00

sim

sim: Remove trailing / from proc/meminfo special path (#689)

2023-12-18 17:28:10 -08:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

systemc: Bugfix in TlmToGem5Bridge (#615)

2023-12-01 16:18:51 -08:00

Doxyfile

misc: Change version information to develop for v24.0

2023-12-27 12:29:52 -08:00

Kconfig

scons: Add new config option HAVE_CAPSTONE to Kconfig

2023-11-23 08:26:11 +08:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00