d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
157 lines
6.2 KiB
Python
157 lines
6.2 KiB
Python
# Copyright (c) 2017, 2019 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# Copyright (c) 2011 Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.DVFSHandler import *
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from m5.objects.SimpleMemory import *
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from m5.objects.Workload import StubWorkload
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from m5.params import *
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from m5.proxy import *
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from m5.SimObject import *
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class MemoryMode(Enum):
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vals = ["invalid", "atomic", "timing", "atomic_noncaching"]
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class System(SimObject):
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type = "System"
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cxx_header = "sim/system.hh"
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cxx_class = "gem5::System"
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system_port = RequestPort("System port")
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cxx_exports = [
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PyBindMethod("getMemoryMode"),
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PyBindMethod("setMemoryMode"),
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]
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memories = VectorParam.AbstractMemory(
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Self.all, "All memories in the system"
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)
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mem_mode = Param.MemoryMode("atomic", "The mode the memory system is in")
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thermal_model = Param.ThermalModel(NULL, "Thermal model")
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thermal_components = VectorParam.SimObject(
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[], "A collection of all thermal components in the system."
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)
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# When reserving memory on the host, we have the option of
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# reserving swap space or not (by passing MAP_NORESERVE to
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# mmap). By enabling this flag, we accommodate cases where a large
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# (but sparse) memory is simulated.
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mmap_using_noreserve = Param.Bool(
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False, "mmap the backing store without reserving swap"
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)
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# The memory ranges are to be populated when creating the system
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# such that these can be passed from the I/O subsystem through an
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# I/O bridge or cache
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mem_ranges = VectorParam.AddrRange(
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[], "Ranges that constitute main memory"
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)
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# The ranges backed by a shadowed ROM
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shadow_rom_ranges = VectorParam.AddrRange(
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[], "Ranges backed by a shadowed ROM"
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)
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shared_backstore = Param.String(
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"",
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"backstore's shmem segment filename, "
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"use to directly address the backstore from another host-OS process. "
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"Leave this empty to unset the MAP_SHARED flag.",
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)
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auto_unlink_shared_backstore = Param.Bool(
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False,
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"Automatically remove the "
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"shmem segment file upon destruction. This is used only if "
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"shared_backstore is non-empty.",
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)
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cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
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redirect_paths = VectorParam.RedirectPath([], "Path redirections")
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exit_on_work_items = Param.Bool(
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False,
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"Exit from the simulation loop when "
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"encountering work item annotations.",
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)
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work_item_id = Param.Int(-1, "specific work item id")
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num_work_ids = Param.Int(16, "Number of distinct work item types")
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work_begin_cpu_id_exit = Param.Int(
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-1, "work started on specific id, now exit simulation"
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)
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work_begin_ckpt_count = Param.Counter(
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0, "create checkpoint when work items begin count value is reached"
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)
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work_begin_exit_count = Param.Counter(
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0, "exit simulation when work items begin count value is reached"
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)
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work_end_ckpt_count = Param.Counter(
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0, "create checkpoint when work items end count value is reached"
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)
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work_end_exit_count = Param.Counter(
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0, "exit simulation when work items end count value is reached"
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)
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work_cpus_ckpt_count = Param.Counter(
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0, "create checkpoint when active cpu count value is reached"
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)
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workload = Param.Workload(StubWorkload(), "Workload to run on this system")
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init_param = Param.UInt64(0, "numerical value to pass into simulator")
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readfile = Param.String("", "file to read startup script from")
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symbolfile = Param.String("", "file to get the symbols from")
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multi_thread = Param.Bool(
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False, "Supports multi-threaded CPUs? Impacts Thread/Context IDs"
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)
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# Dynamic voltage and frequency handler for the system, disabled by default
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# Provide list of domains that need to be controlled by the handler
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dvfs_handler = DVFSHandler()
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# SE mode doesn't use the ISA System subclasses, and so we need to set an
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# ISA specific value in this class directly.
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m5ops_base = Param.Addr(
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0,
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"Base of the 64KiB PA range used for "
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"memory-mapped m5ops. Set to 0 to disable.",
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)
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