Mitch Hayenga 582a0148b4 config,cpu: Add SMT support to Atomic and Timing CPUs ...

Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.

2015-09-30 11:14:19 -05:00

..

fs.py

config: Support full-system with SST's memory system

2015-04-08 15:56:06 -05:00

memcheck.py

mem: Add explicit Cache subclass and make BaseCache abstract

2015-08-21 07:03:23 -04:00

memtest.py

mem: Add explicit Cache subclass and make BaseCache abstract

2015-08-21 07:03:23 -04:00

read_config.py

config: Add the ability to read a config file using C++ and Python

2014-10-16 05:49:37 -04:00

ruby_direct_test.py

ruby: interface with classic memory controller

2014-11-06 05:42:21 -06:00

ruby_mem_test.py

mem: Move crossbar default latencies to subclasses

2015-03-02 04:00:47 -05:00

ruby_network_test.py

configs: network test: remove redundant physical memory

2015-07-21 10:08:25 -05:00

ruby_random_test.py

ruby: interface with classic memory controller

2014-11-06 05:42:21 -06:00

se.py

config,cpu: Add SMT support to Atomic and Timing CPUs

2015-09-30 11:14:19 -05:00