Steve Reinhardt 57ff2604e5 Minor fix plus new assertion to catch similar bugs. ...

src/cpu/memtest/memtest.cc:
    Need to set packet source field so that response from cache
    doesn't run into assertion failure when copying source to dest.
src/mem/packet.hh:
    Copy source field when copying packets.
    Assert that source is valid before copying it to dest
    when turning packets around.

--HG--
extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8

2007-06-23 13:24:33 -07:00

..

cache

Fixes to hitLatency, blocking, buffer allocation.

2007-06-22 09:24:07 -07:00

config

Backing in more changsets, getting closer to compile

2006-06-28 14:35:00 -04:00

bridge.cc

More major reorg of cache. Seems to work for atomic mode now,

2007-06-17 17:27:53 -07:00

bridge.hh

Change getDeviceAddressRanges to use bool for snoop arg.

2007-05-21 23:36:09 -07:00

Bridge.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

bus.cc

Merge vm1.(none):/home/stever/bk/newmem-head

2007-06-21 12:03:22 -07:00

bus.hh

Merge vm1.(none):/home/stever/bk/newmem-head

2007-06-17 17:30:24 -07:00

Bus.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

dram.cc

make our code a little more standards compliant

2007-01-26 18:48:51 -05:00

dram.hh

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

mem_object.cc

stop m5 from leaking like a sieve

2007-03-08 18:57:15 -05:00

mem_object.hh

stop m5 from leaking like a sieve

2007-03-08 18:57:15 -05:00

MemObject.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

packet_access.hh

Make byteswap work correctly on Twin??_t types.

2007-03-07 17:46:04 +00:00

packet.cc

Getting closer...

2007-06-21 11:59:17 -07:00

packet.hh

Minor fix plus new assertion to catch similar bugs.

2007-06-23 13:24:33 -07:00

page_table.cc

Clean up some of vincent's code and commit it

2007-06-05 01:03:35 -04:00

page_table.hh

Clean up some of vincent's code and commit it

2007-06-05 01:03:35 -04:00

physical.cc

More major reorg of cache. Seems to work for atomic mode now,

2007-06-17 17:27:53 -07:00

physical.hh

More major reorg of cache. Seems to work for atomic mode now,

2007-06-17 17:27:53 -07:00

PhysicalMemory.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

port_impl.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

port.cc

The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter.

2007-04-04 13:56:38 -04:00

port.hh

Change getDeviceAddressRanges to use bool for snoop arg.

2007-05-21 23:36:09 -07:00

request.hh

Use FastAlloc for Packet, Request, CoherenceState, and SenderState so we don't spend so much time calling malloc()

2007-06-21 13:50:35 -04:00

SConscript

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

tport.cc

More major reorg of cache. Seems to work for atomic mode now,

2007-06-17 17:27:53 -07:00

tport.hh

A little more cleanup & refactoring of SimpleTimingPort.

2007-05-29 22:23:41 -07:00

translating_port.cc

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

translating_port.hh

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

vport.cc

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00

vport.hh

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00