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gem5/src/sim
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Steve Reinhardt bd4ccd6e39 Finish test clean-up & reorg. 
configs/common/FSConfig.py:
    Add default Machine() param
configs/example/fs.py:
configs/example/se.py:
    make it work again
src/python/m5/objects/BaseCPU.py:
    Make mem PhysicalMemory so that a Parent.any proxy works well
src/sim/process.cc:
    Increase default stack size so we don't get an
    'increasing stack' message on 'hello world'
tests/SConscript:
    Add full list of current configs.
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
    don't need SEConfig anymore
tests/quick/00.hello/test.py:
tests/quick/20.eio-short/test.py:
    fix
tests/run.py:
    move configs to separate dir

--HG--
rename : configs/test/fs.py => configs/example/fs.py
rename : configs/test/test.py => configs/example/se.py
rename : tests/simple-atomic.py => tests/configs/simple-atomic.py
rename : tests/simple-timing.py => tests/configs/simple-timing.py
rename : tests/linux-mpboot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
rename : tests/linux-mpboot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
rename : tests/linux-mpboot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
rename : tests/linux-boot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
rename : tests/linux-boot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
rename : tests/linux-boot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
rename : tests/linux-boot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
rename : tests/linux-boot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
rename : tests/linux-boot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
rename : tests/linux-mpboot/ref/alpha/timing/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/timing/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
rename : tests/linux-mpboot/ref/alpha/timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
rename : tests/linux-mpboot/ref/alpha/timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
rename : tests/test-progs/hello/bin/mips/linux/hello_mips => tests/test-progs/hello/bin/mips/linux/hello
rename : tests/test-progs/hello/bin/sparc/bin => tests/test-progs/hello/bin/sparc/linux/hello
extra : convert_revision : d68ee6d7eefa7ba57370f3fb3c3589f86a6ea6b4
2006-08-16 14:42:44 -04:00
..
async.hh
Updated Authors from bk prs info
2006-05-31 19:26:56 -04:00
builder.cc
Move SimObject creation and Port connection loops
2006-06-13 23:19:28 -04:00
builder.hh
fixes for gcc 4.1
2006-08-15 17:41:22 -04:00
byteswap.hh
Added myself to the authors list.
2006-07-23 03:04:46 -04:00
debug.cc
remove extern "C" from the functions we all from gdb. This isn't requried and trips up GDB sometimes when i thinks the extern
2006-06-26 17:49:49 -04:00
debug.hh
Updated Authors from bk prs info
2006-05-31 19:26:56 -04:00
eventq.cc
Move main control from C++ into Python.
2006-06-09 23:01:31 -04:00
eventq.hh
Move main control from C++ into Python.
2006-06-09 23:01:31 -04:00
faults.cc
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
2006-06-06 17:32:21 -04:00
faults.hh
add syscall emulation page table fault so we can allocate more stack pages
2006-06-26 16:49:05 -04:00
host.hh
Move main control from C++ into Python.
2006-06-09 23:01:31 -04:00
main.cc
Get the path to load the ini file from. I'm not sure if this fix is needed in other places as well.
2006-07-19 15:28:53 -04:00
param.cc
Move SimObject creation and Port connection loops
2006-06-13 23:19:28 -04:00
param.hh
Move SimObject creation and Port connection loops
2006-06-13 23:19:28 -04:00
process.cc
Finish test clean-up & reorg.
2006-08-16 14:42:44 -04:00
process.hh
Move LiveProcess::create() from arch-specific files
2006-06-11 21:49:46 -04:00
pseudo_inst.cc
Two minor FS compile fixes.
2006-07-06 16:26:44 -04:00
pseudo_inst.hh
Cleaned up include files and got rid of many using directives in header files.
2006-08-15 05:07:15 -04:00
root.cc
Move main control from C++ into Python.
2006-06-09 23:01:31 -04:00
serialize.cc
Take the name of the checkpoint directory in when calling checkpoint() or restoreCheckpoint().
2006-07-07 16:46:08 -04:00
serialize.hh
Take the name of the checkpoint directory in when calling checkpoint() or restoreCheckpoint().
2006-07-07 16:46:08 -04:00
sim_events.cc
Rename quiesce to drain to avoid confusion with the pseudo instruction.
2006-07-05 17:59:33 -04:00
sim_events.hh
Rename quiesce to drain to avoid confusion with the pseudo instruction.
2006-07-05 17:59:33 -04:00
sim_exit.hh
Move main control from C++ into Python.
2006-06-09 23:01:31 -04:00
sim_object.cc
memory mode information now contained in system object
2006-07-12 20:22:07 -04:00
sim_object.hh
memory mode information now contained in system object
2006-07-12 20:22:07 -04:00
startup.cc
Updated Authors from bk prs info
2006-05-31 19:26:56 -04:00
startup.hh
Updated Authors from bk prs info
2006-05-31 19:26:56 -04:00
stat_control.cc
remove extern "C" from the functions we all from gdb. This isn't requried and trips up GDB sometimes when i thinks the extern
2006-06-26 17:49:49 -04:00
stat_control.hh
Updated Authors from bk prs info
2006-05-31 19:26:56 -04:00
stats.hh
Updated Authors from bk prs info
2006-05-31 19:26:56 -04:00
syscall_emul.cc
Fix for FS O3CPU compile ... missing forward class declaration/header file after files got split for ISA-independence
2006-07-03 12:19:35 -04:00
syscall_emul.hh
Fix so that O3CPU doesnt segfault on exit.
2006-07-07 04:06:26 -04:00
system.cc
add system.mem_mode = ['timing', 'atomic']
2006-07-13 15:48:17 -04:00
system.hh
fixes for gcc 4.1
2006-08-15 17:41:22 -04:00
vptr.hh
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
2006-06-06 17:32:21 -04:00