1d755b4ba1
isa_traits.hh used to have much more in it, but now it only has PageShift, PageBytes, and (for now) the guest endianness. These values should only be retrieved from the System class generally speaking, so only the system class should include arch/isa_traits.hh. Some gpu compute related files need PageBytes or PageShift. Even though those files don't advertise their ISA dependence, they are tied to x86. In those files, they can include arch/x86/isa_traits.hh. The only other file which legitimately needs arch/isa_traits.hh is the decoder cache since it uses PageBytes to size an array. Change-Id: I12686368715623e3140a68a7027c136bd52567b1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33203 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
83 lines
3.1 KiB
C++
83 lines
3.1 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_IMPL_HH__
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#define __CPU_O3_IMPL_HH__
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#include "config/the_isa.hh"
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#include "cpu/o3/cpu_policy.hh"
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// Forward declarations.
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template <class Impl>
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class BaseO3DynInst;
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template <class Impl>
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class FullO3CPU;
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/** Implementation specific struct that defines several key types to the
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* CPU, the stages within the CPU, the time buffers, and the DynInst.
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* The struct defines the ISA, the CPU policy, the specific DynInst, the
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* specific O3CPU, and all of the structs from the time buffers to do
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* communication.
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* This is one of the key things that must be defined for each hardware
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* specific CPU implementation.
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*/
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struct O3CPUImpl
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{
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/** The type of MachInst. */
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typedef TheISA::MachInst MachInst;
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/** The CPU policy to be used, which defines all of the CPU stages. */
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typedef SimpleCPUPolicy<O3CPUImpl> CPUPol;
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/** The DynInst type to be used. */
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typedef BaseO3DynInst<O3CPUImpl> DynInst;
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/** The refcounted DynInst pointer to be used. In most cases this is
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* what should be used, and not DynInst *.
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*/
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typedef RefCountingPtr<DynInst> DynInstPtr;
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typedef RefCountingPtr<const DynInst> DynInstConstPtr;
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/** The O3CPU type to be used. */
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typedef FullO3CPU<O3CPUImpl> O3CPU;
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/** Same typedef, but for CPUType. BaseDynInst may not always use
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* an O3 CPU, so it's clearer to call it CPUType instead in that
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* case.
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*/
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typedef O3CPU CPUType;
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enum {
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MaxWidth = 8,
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MaxThreads = 4
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};
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};
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#endif // __CPU_O3_SPARC_IMPL_HH__
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