569e21f798
`get_runtime_isa()` has been deprecated for some time. It is a leftover piece of code from when gem5 was compiled to a single ISA and that ISA used to configure the simulated system to use that ISA. Since multi-ISA compilations are possible, `get_runtime_isa()` should not be used. Unless the gem5 binary is compiled to a single ISA, a failure will occur. The new proceedure for specify which ISA to use is by the setting of the correct `BaseCPU` implementation. E.g., `X86SimpleTimingCPU` of `ArmO3CPU`. This patch removes the remaining `get_runtime_isa()` instances and removes the function itself. The `SimpleCore` class has been updated to allow for it's CPU factory to return a class, needed by scripts in "configs/common". The deprecated functionality in the standard library, which allowed for the specifying of an ISA when setting up a processor and/or core has also been removed. Setting an ISA is now manditory. Fixes #216.
102 lines
3.5 KiB
Python
102 lines
3.5 KiB
Python
# Copyright (c) 2017, University of Kaiserslautern
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Éder F. Zulian
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import argparse
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import sys
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import m5
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from m5.objects import *
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from m5.util import *
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addToPath("../")
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from common import (
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HMC,
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MemConfig,
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ObjectList,
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)
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pd = "Simple 'hello world' example using HMC as main memory"
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parser = argparse.ArgumentParser(description=pd)
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parser.add_argument(
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"--cpu-type",
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type=str,
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default="X86TimingSimpleCPU",
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choices=ObjectList.CPUList().get_names(),
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help="CPU model to use",
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)
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HMC.add_options(parser)
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options = parser.parse_args()
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# create the system we are going to simulate
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system = System()
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# use timing mode for the interaction between requestor-responder ports
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system.mem_mode = "timing"
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# set the clock frequency of the system
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clk = "1GHz"
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vd = VoltageDomain(voltage="1V")
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system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
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# create a CPU
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system.cpu = ObjectList().get(options.cpu_type)()
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# config memory system
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MemConfig.config_mem(options, system)
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# hook the CPU ports up to the membus
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system.cpu.icache_port = system.membus.cpu_side_ports
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system.cpu.dcache_port = system.membus.cpu_side_ports
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# create the interrupt controller for the CPU and connect to the membus
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system.cpu.createInterruptController()
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# connect special port in the system to the membus. This port is a
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# functional-only port to allow the system to read and write memory.
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system.system_port = system.membus.cpu_side_ports
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# run 'hello' and use the compiled ISA to find the binary
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binary = (
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"tests/test-progs/hello/bin/"
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+ ObjectList.CPUList().get_isa(options.cpu_type).name.lower()
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+ "/linux/hello"
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)
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# create a process for a simple "Hello World" application
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process = Process()
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# cmd is a list which begins with the executable (like argv)
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process.cmd = [binary]
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# set the system workload
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system.workload = SEWorkload.init_compatible(binary)
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# set the cpu workload
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system.cpu.workload = process
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# create thread contexts
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system.cpu.createThreads()
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# set up the root SimObject
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root = Root(full_system=False, system=system)
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m5.instantiate()
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m5.simulate()
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