55f5c4dd8a
The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Add the Master Port. Add an example application that isslustrates its * use. Testing Done: A simple example application consisting of a TLM traffic generator and a gem5 memory is part of the patch. Reviewed at http://reviews.gem5.org/r/3528/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
138 lines
4.7 KiB
C++
138 lines
4.7 KiB
C++
/*
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Christian Menard
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*/
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#ifndef __SC_MASTER_PORT_HH__
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#define __SC_MASTER_PORT_HH__
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#include <tlm_utils/peq_with_cb_and_phase.h>
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#include <tlm_utils/simple_target_socket.h>
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#include <tlm>
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#include <mem/external_master.hh>
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#include <sc_module.hh>
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#include <sc_peq.hh>
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namespace Gem5SystemC
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{
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/**
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* This is a gem5 master port that translates TLM transactions to gem5 packets.
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*
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* Upon receiving a TLM transaction (b_transport, nb_transport_fw,
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* dbg_transport) the port generates a gem5 packet and initializes the packet
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* with information from the transaction payload. The original TLM payload is
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* added as a sender state to the gem5 packet. This way the payload can be
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* restored when the response packet arrives at the port.
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*
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* If gem5 operates in atomic mode, the master port registers the TLM blocking
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* interface and automatically translates non-blocking requests to blocking.
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* If gem5 operates in timing mode, the transactor registers the non-blocking
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* interface. Then, the transactor automatically translated blocking requests.
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* It is assumed that the mode (atomic/timing) does not change during
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* execution.
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*/
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class SCMasterPort : public ExternalMaster::Port
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{
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private:
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struct TlmSenderState : public Packet::SenderState
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{
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tlm::tlm_generic_payload& trans;
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TlmSenderState(tlm::tlm_generic_payload& trans)
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: trans(trans)
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{
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}
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};
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tlm_utils::peq_with_cb_and_phase<SCMasterPort> peq;
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bool waitForRetry;
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tlm::tlm_generic_payload* pendingRequest;
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bool needToSendRetry;
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bool responseInProgress;
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// Keep a reference to the gem5 SystemC module
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Module& module;
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public:
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tlm_utils::simple_target_socket<SCMasterPort> tSocket;
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protected:
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// payload event call back
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void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
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// The TLM target interface
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tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
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tlm::tlm_phase& phase,
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sc_core::sc_time& t);
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void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& t);
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unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
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bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
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tlm::tlm_dmi& dmi_data);
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// Gem5 SCMasterPort interface
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bool recvTimingResp(PacketPtr pkt);
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void recvReqRetry();
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void recvRangeChange();
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public:
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SCMasterPort(const std::string& name_,
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const std::string& systemc_name,
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ExternalMaster& owner_,
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Module& module);
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static void registerPortHandler(Module& module);
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friend PayloadEvent<SCMasterPort>;
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private:
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void sendEndReq(tlm::tlm_generic_payload& trans);
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void sendBeginResp(tlm::tlm_generic_payload& trans,
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sc_core::sc_time& delay);
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void handleBeginReq(tlm::tlm_generic_payload& trans);
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void handleEndResp(tlm::tlm_generic_payload& trans);
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PacketPtr generatePacket(tlm::tlm_generic_payload& trans);
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void destroyPacket(PacketPtr pkt);
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void checkTransaction(tlm::tlm_generic_payload& trans);
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};
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}
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#endif
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