403817cd0d
Previously, the RISC-V devices queried the system object in SimObject::init() for the number of CPUs and the number of threads. However, the system object doesn't actually count the number of CPUs/threads until it runs init(). Therefore, we've just been getting lucky in the order that the SimObject init() functions were called. This change instead decouples these two functions and makes the number of CPUs/threads a parameter for the RISC-V interrupt devices. This change also updates the example config script. Change-Id: Ic4da5604156837cfeec05e58d188b42a02420de1 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49431 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
83 lines
3.7 KiB
Python
83 lines
3.7 KiB
Python
# Copyright (c) 2021 Huawei International
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.Device import BasicPioDevice
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from m5.params import *
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from m5.proxy import *
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from m5.util.fdthelper import *
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class Plic(BasicPioDevice):
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"""
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This implementation of PLIC is based on
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the SiFive U54MC datasheet:
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https://sifive.cdn.prismic.io/sifive/fab000f6-
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0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_
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full_20G1.03.00_manual.pdf
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"""
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type = 'Plic'
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cxx_header = 'dev/riscv/plic.hh'
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cxx_class = 'gem5::Plic'
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pio_size = Param.Addr(0x4000000, "PIO Size")
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n_src = Param.Int("Number of interrupt sources")
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n_contexts = Param.Int("Number of interrupt contexts. Usually the number "
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"of threads * 2. One for M mode, one for S mode")
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def generateDeviceTree(self, state):
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node = self.generateBasicPioDeviceNode(state, "plic", self.pio_addr,
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self.pio_size)
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int_state = FdtState(addr_cells=0, interrupt_cells=1)
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node.append(int_state.addrCellsProperty())
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node.append(int_state.interruptCellsProperty())
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phandle = int_state.phandle(self)
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node.append(FdtPropertyWords("phandle", [phandle]))
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node.append(FdtPropertyWords("riscv,ndev", [self.n_src - 1]))
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cpus = self.system.unproxy(self).cpu
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int_extended = list()
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for cpu in cpus:
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phandle = int_state.phandle(cpu)
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int_extended.append(phandle)
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int_extended.append(0xb)
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int_extended.append(phandle)
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int_extended.append(0x9)
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node.append(FdtPropertyWords("interrupts-extended", int_extended))
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node.append(FdtProperty("interrupt-controller"))
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node.appendCompatible(["riscv,plic0"])
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yield node
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