Giacomo Gabrielli c4cc3145cd arch-arm,cpu: Add initial support for Arm SVE ...

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2019-03-14 10:42:27 +00:00

..

arm-ccregs.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

arm-contextidr-el2.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

arm-gem5-gic-ext.py

dev, arm: Add gem5 extensions to support more than 8 cores

2015-09-18 16:49:28 +01:00

arm-gicv2-banked-regs.py

arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling

2017-04-03 16:51:46 +00:00

arm-hdlcd-upgrade.py

dev, arm: Rewrite the HDLCD controller

2015-09-11 15:55:46 +01:00

arm-miscreg-teehbr.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

arm-sve.py

arch-arm,cpu: Add initial support for Arm SVE

2019-03-14 10:42:27 +00:00

arm-sysreg-mapping-ns.py

arm: update AArch{64,32} register mappings

2016-12-19 11:03:27 -06:00

armv8.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

cpu-pid.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

dvfs-perflevel.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

etherswitch.py

dist, dev: fix etherswitch upgrade script

2016-12-19 12:12:28 -06:00

ide-dma-abort.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

isa-is-simobject.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

memory-per-range.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

multiple-event-queues.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

process-fdmap-rename.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

remove-arm-cpsr-mode-miscreg.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

ruby-block-size-bytes.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

smt-interrupts.py

isa,cpu: Add support for FS SMT Interrupts

2015-09-30 11:14:19 -05:00

x86-add-tlb.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00