68b6f9c8a1
This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
100 lines
3.2 KiB
C++
100 lines
3.2 KiB
C++
/*
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* Copyright (c) 2016 RISC-V Foundation
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* Copyright (c) 2016 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Alec Roelke
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*/
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#include "arch/riscv/faults.hh"
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#include "arch/riscv/utility.hh"
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#include "cpu/thread_context.hh"
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#include "sim/debug.hh"
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#include "sim/full_system.hh"
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using namespace RiscvISA;
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void
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RiscvFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
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{
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panic("Fault %s encountered at pc 0x%016llx.", name(), tc->pcState().pc());
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}
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void
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RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
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{
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if (FullSystem) {
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panic("Full system mode not supported for RISC-V.");
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} else {
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invoke_se(tc, inst);
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PCState pcState = tc->pcState();
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advancePC(pcState, inst);
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tc->pcState(pcState);
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}
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}
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void
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UnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
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{
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panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst,
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tc->pcState().pc());
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}
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void
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IllegalInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
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{
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panic("Illegal instruction 0x%08x at pc 0x%016llx: %s", inst->machInst,
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tc->pcState().pc(), reason.c_str());
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}
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void
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UnimplementedFault::invoke_se(ThreadContext *tc,
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const StaticInstPtr &inst)
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{
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panic("Unimplemented instruction %s at pc 0x%016llx", instName,
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tc->pcState().pc());
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}
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void
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IllegalFrmFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
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{
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panic("Illegal floating-point rounding mode 0x%x at pc 0x%016llx.",
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frm, tc->pcState().pc());
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}
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void
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BreakpointFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
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{
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schedRelBreak(0);
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}
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void
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SyscallFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
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{
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Fault *fault = NoFault;
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tc->syscall(tc->readIntReg(SyscallNumReg), fault);
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}
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