Andreas Hansson 54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width ...

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

2012-10-15 08:09:54 -04:00

..

configs

Regression: Use addTwoLevelCacheHierarchy in configs

2012-10-15 08:07:09 -04:00

long

Stats: Update stats for new default L1-to-L2 bus clock and width

2012-10-15 08:09:54 -04:00

quick

Stats: Update stats for new default L1-to-L2 bus clock and width

2012-10-15 08:09:54 -04:00

test-progs/hello

X86: Add a 32 bit hello world test binary.

2012-05-27 19:01:09 -07:00

diff-out

tests: fix diff-out script for op/inst stat changes.

2012-02-12 18:35:59 -06:00

halt.sh

Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.

2006-07-21 15:56:35 -04:00

run.py

SE/FS: Make both SE and FS tests available all the time.

2012-01-28 07:24:45 -08:00

SConscript

SimpleDRAM: A basic SimpleDRAM regression

2012-09-21 11:48:14 -04:00