cb8856f580
The stride prefetcher had a hardcoded number of contexts (i.e. master-IDs) that it could handle. Since master IDs need to be unique per system, and every core, cache etc. requires a separate master port, a static limit on these does not make much sense. Instead, this patch adds a small hash map that will map all master IDs to the right prefetch state and dynamically allocates new state for new master IDs.
120 lines
4.0 KiB
C++
120 lines
4.0 KiB
C++
/*
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* Copyright (c) 2012-2013, 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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*/
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/**
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* @file
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* Describes a strided prefetcher.
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*/
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#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__
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#define __MEM_CACHE_PREFETCH_STRIDE_HH__
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#include "base/hashmap.hh"
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#include "mem/cache/prefetch/queued.hh"
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#include "params/StridePrefetcher.hh"
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class StridePrefetcher : public QueuedPrefetcher
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{
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protected:
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const int maxConf;
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const int threshConf;
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const int minConf;
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const int startConf;
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const int pcTableAssoc;
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const int pcTableSets;
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const bool useMasterId;
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const int degree;
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struct StrideEntry
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{
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StrideEntry() : instAddr(0), lastAddr(0), isSecure(false), stride(0),
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confidence(0)
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{ }
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Addr instAddr;
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Addr lastAddr;
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bool isSecure;
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int stride;
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int confidence;
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};
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class PCTable
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{
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public:
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PCTable(int assoc, int sets, const std::string name) :
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pcTableAssoc(assoc), pcTableSets(sets), _name(name) {}
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StrideEntry** operator[] (int context) {
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auto it = entries.find(context);
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if (it != entries.end())
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return it->second;
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return allocateNewContext(context);
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}
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~PCTable();
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private:
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const std::string name() {return _name; }
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const int pcTableAssoc;
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const int pcTableSets;
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const std::string _name;
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m5::hash_map<int, StrideEntry**> entries;
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StrideEntry** allocateNewContext(int context);
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};
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PCTable pcTable;
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bool pcTableHit(Addr pc, bool is_secure, int master_id, StrideEntry* &entry);
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StrideEntry* pcTableVictim(Addr pc, int master_id);
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Addr pcHash(Addr pc) const;
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public:
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StridePrefetcher(const StridePrefetcherParams *p);
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void calculatePrefetch(const PacketPtr &pkt, std::vector<Addr> &addresses);
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};
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#endif // __MEM_CACHE_PREFETCH_STRIDE_HH__
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