52b3f58a8c
Change-Id: I2a165d3130c1464a73823046e4c7b03ba0355459 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25457 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
98 lines
4.0 KiB
ArmAsm
98 lines
4.0 KiB
ArmAsm
/*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <gem5/asm/generic/m5ops.h>
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#if defined(M5OP_ADDR) && defined(M5OP_PIC)
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/* Use the memory mapped m5op interface */
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#define TWO_BYTE_OP(name, number) \
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.globl name; \
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.func name; \
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name: \
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mov m5_mem@gotpcrel(%rip), %r11; \
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mov (%r11), %r11; \
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mov $number, %rax; \
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shl $8, %rax; \
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mov 0(%r11, %rax, 1), %rax; \
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ret; \
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.endfunc;
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#elif defined(M5OP_ADDR) && !defined(M5OP_PIC)
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/* Use the memory mapped m5op interface */
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#define TWO_BYTE_OP(name, number) \
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.globl name; \
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.func name; \
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name: \
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mov m5_mem, %r11; \
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mov $number, %rax; \
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shl $8, %rax; \
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mov 0(%r11, %rax, 1), %rax; \
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ret; \
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.endfunc;
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#else
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/* Use the magic instruction based m5op interface. This does not work
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* in virtualized environments.
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*/
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#define TWO_BYTE_OP(name, number) \
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.globl name; \
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.func name; \
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name: \
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.byte 0x0F, 0x04; \
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.word number; \
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ret; \
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.endfunc;
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#endif
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TWO_BYTE_OP(m5_arm, M5OP_ARM)
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TWO_BYTE_OP(m5_quiesce, M5OP_QUIESCE)
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TWO_BYTE_OP(m5_quiesce_ns, M5OP_QUIESCE_NS)
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TWO_BYTE_OP(m5_quiesce_cycle, M5OP_QUIESCE_CYCLE)
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TWO_BYTE_OP(m5_quiesce_time, M5OP_QUIESCE_TIME)
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TWO_BYTE_OP(m5_rpns, M5OP_RPNS)
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TWO_BYTE_OP(m5_wake_cpu, M5OP_WAKE_CPU)
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TWO_BYTE_OP(m5_exit, M5OP_EXIT)
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TWO_BYTE_OP(m5_fail, M5OP_FAIL)
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TWO_BYTE_OP(m5_init_param, M5OP_INIT_PARAM)
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TWO_BYTE_OP(m5_load_symbol, M5OP_LOAD_SYMBOL)
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TWO_BYTE_OP(m5_reset_stats, M5OP_RESET_STATS)
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TWO_BYTE_OP(m5_dump_stats, M5OP_DUMP_STATS)
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TWO_BYTE_OP(m5_dump_reset_stats, M5OP_DUMP_RESET_STATS)
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TWO_BYTE_OP(m5_checkpoint, M5OP_CHECKPOINT)
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TWO_BYTE_OP(m5_read_file, M5OP_READ_FILE)
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TWO_BYTE_OP(m5_write_file, M5OP_WRITE_FILE)
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TWO_BYTE_OP(m5_debug_break, M5OP_DEBUG_BREAK)
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TWO_BYTE_OP(m5_switch_cpu, M5OP_SWITCH_CPU)
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TWO_BYTE_OP(m5_add_symbol, M5OP_ADD_SYMBOL)
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TWO_BYTE_OP(m5_panic, M5OP_PANIC)
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TWO_BYTE_OP(m5_work_begin, M5OP_WORK_BEGIN)
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TWO_BYTE_OP(m5_work_end, M5OP_WORK_END)
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TWO_BYTE_OP(m5_dist_toggle_sync, M5OP_DIST_TOGGLE_SYNC)
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