ab309b9e4e
Moved the dcache check to the LLSC functions that use it. This allows a Sequencer to be coupled with a gem5 object that does not need a cache (as long as it doesn't issue LLSC instructions). Also, icache was not used at all so it was removed. Change-Id: I04bd2711f8d0a7dfc952cff8e0020d2d1881cae1 Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31267 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Bradford Beckmann <bradford.beckmann@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
115 lines
4.5 KiB
Python
115 lines
4.5 KiB
Python
# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# Copyright (c) 2016 Georgia Institute of Technology
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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from .Ruby import create_topology, create_directories
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#
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# Declare caches used by the protocol
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#
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class L1Cache(RubyCache): pass
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def define_options(parser):
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return
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def create_system(options, full_system, system, dma_ports, bootmem,
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ruby_system):
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if buildEnv['PROTOCOL'] != 'Garnet_standalone':
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panic("This script requires Garnet_standalone protocol to be built.")
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cpu_sequencers = []
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#
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# The Garnet_standalone protocol does not support fs nor dma
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#
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assert(dma_ports == [])
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list.
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# Therefore the l1 controller nodes must be listed before
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# the directory nodes and directory nodes before dma nodes, etc.
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l1_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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for i in range(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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# Only one cache exists for this protocol, so by default use the L1D
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# config parameters.
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#
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cache = L1Cache(size = options.l1d_size,
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assoc = options.l1d_assoc)
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#
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# Only one unified L1 cache exists. Can cache instructions and data.
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#
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l1_cntrl = L1Cache_Controller(version = i,
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cacheMemory = cache,
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(dcache = cache,
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garnet_standalone = True,
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ruby_system = ruby_system)
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l1_cntrl.sequencer = cpu_seq
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exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
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# Add controllers and sequencers to the appropriate lists
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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# Connect the L1 controllers and the network
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l1_cntrl.mandatoryQueue = MessageBuffer()
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l1_cntrl.requestFromCache = MessageBuffer()
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l1_cntrl.responseFromCache = MessageBuffer()
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l1_cntrl.forwardFromCache = MessageBuffer()
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mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
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options, bootmem, ruby_system, system)
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dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
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if rom_dir_cntrl_node is not None:
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dir_cntrl_nodes.append(rom_dir_cntrl_node)
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for dir_cntrl in dir_cntrl_nodes:
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# Connect the directory controllers and the network
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dir_cntrl.requestToDir = MessageBuffer()
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dir_cntrl.forwardToDir = MessageBuffer()
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dir_cntrl.responseToDir = MessageBuffer()
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all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes
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ruby_system.network.number_of_virtual_networks = 3
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topology = create_topology(all_cntrls, options)
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return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
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