4f7b3ed827
There are several parts to this PR to work towards #1349 . (1) Make RubySystem::getBlockSizeBytes non-static by providing ways to access the block size or passing the block size explicitly to classes. The main changes are: - DataBlocks must be explicitly allocated. A default ctor still exists to avoid needing to heavily modify SLICC. The size can be set using a realloc function, operator=, or copy ctor. This is handled completely transparently meaning no protocol or config changes are required. - WriteMask now requires block size to be set. This is also handled transparently by modifying the SLICC parser to identify WriteMask types and call setBlockSize(). - AbstractCacheEntry and TBE classes now require block size to be set. This is handled transparently by modifying the SLICC parser to identify these classes and call initBlockSize() which calls setBlockSize() for any DataBlock or WriteMask. - All AbstractControllers now have a pointer to RubySystem. This is assigned in SLICC generated code and requires no changes to protocol or configs. - The Ruby Message class now requires block size in all constructors. This is added to the argument list automatically by the SLICC parser. (2) Relax dependence on common functions in src/mem/ruby/common/Address.hh so that RubySystem::getBlockSizeBits is no longer static. Many classes already have a way to get block size from the previous commit, so they simply multiple by 8 to get the number of bits. For handling SLICC and reducing the number of changes, define makeCacheLine, getOffset, etc. in RubyPort and AbstractController. The only protocol changes required are to change any "RubySystem::foo()" calls with "m_ruby_system->foo()". For classes which do not have a way to get access to block size but still used makeLineAddress, getOffset, etc., the block size must be passed to that class. This requires some changes to the SimObject interface for two commonly used classes: DirectoryMemory and RubyPrefecther, resulting in user-facing API changes User-facing API changes: - DirectoryMemory and RubyPrefetcher now require the cache line size as a non-optional argument. - RubySequencer SimObjects now require RubySystem as a non-optional argument. - TesterThread in the GPU ruby tester now requires the cache line size as a non-optional argument. (3) Removes static member variables in RubySystem which control randomization, cooldown, and warmup. These are mostly used by the Ruby Network. The network classes are modified to take these former static variables as parameters which are passed to the corresponding method (e.g., enqueue, delayHead, etc.) rather than needing a RubySystem object at all. Change-Id: Ia63c2ad5cf0bf9d1cbdffba5d3a679bb4d3b1220 (4) There are two major SLICC generated static methods: getNumControllers() on each cache controller which returns the number of controllers created by the configs at run time and the functions which access this method, which are MachineType_base_count and MachineType_base_number. These need to be removed to create multiple RubySystem objects otherwise NetDest, version value, and other objects are incorrect. To remove the static requirement, MachineType_base_count and MachineType_base_number are moved to RubySystem. Any class which needs to call these methods must now have a pointer to a RubySystem. To enable that, several changes are made: - RubyRequest and Message now require a RubySystem pointer in the constructor. The pointer is passed to fields in the Message class which require a RubySystem pointer (e.g., NetDest). SLICC is modified to do this automatically. - SLICC structures may now optionally take an "implicit constructor" which can be used to call a non-default constructor for locally defined variables (e.g., temporary variables within SLICC actions). A statement such as "NetDest bcast_dest;" in SLICC will implicitly append a call to the NetDest constructor taking RubySystem, for example. - RubySystem gets passed to Ruby network objects (Network, Topology).
439 lines
14 KiB
Python
439 lines
14 KiB
Python
# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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import math
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from common import FileSystemConfig
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import addToPath
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from .Ruby import (
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create_topology,
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send_evicts,
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)
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addToPath("../")
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from topologies.Cluster import Cluster
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from topologies.Crossbar import Crossbar
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class CntrlBase:
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_seqs = 0
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@classmethod
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def seqCount(cls):
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# Use SeqCount not class since we need global count
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CntrlBase._seqs += 1
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return CntrlBase._seqs - 1
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_cntrls = 0
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@classmethod
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def cntrlCount(cls):
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# Use CntlCount not class since we need global count
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CntrlBase._cntrls += 1
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return CntrlBase._cntrls - 1
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_version = 0
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@classmethod
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def versionCount(cls):
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cls._version += 1 # Use count for this particular type
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return cls._version - 1
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class L1DCache(RubyCache):
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resourceStalls = False
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def create(self, options):
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self.size = MemorySize(options.l1d_size)
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self.assoc = options.l1d_assoc
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self.replacement_policy = TreePLRURP()
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class L1ICache(RubyCache):
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resourceStalls = False
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def create(self, options):
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self.size = MemorySize(options.l1i_size)
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self.assoc = options.l1i_assoc
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self.replacement_policy = TreePLRURP()
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class L2Cache(RubyCache):
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resourceStalls = False
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def create(self, options):
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self.size = MemorySize(options.l2_size)
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self.assoc = options.l2_assoc
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self.replacement_policy = TreePLRURP()
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class CPCntrl(CorePair_Controller, CntrlBase):
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def create(self, options, ruby_system, system):
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self.version = self.versionCount()
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self.L1Icache = L1ICache()
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self.L1Icache.create(options)
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self.L1D0cache = L1DCache()
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self.L1D0cache.create(options)
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self.L1D1cache = L1DCache()
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self.L1D1cache.create(options)
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self.L2cache = L2Cache()
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self.L2cache.create(options)
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self.sequencer = RubySequencer(ruby_system=ruby_system)
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self.sequencer.version = self.seqCount()
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self.sequencer.dcache = self.L1D0cache
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self.sequencer.ruby_system = ruby_system
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self.sequencer.coreid = 0
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self.sequencer.is_cpu_sequencer = True
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self.sequencer1 = RubySequencer(ruby_system=ruby_system)
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self.sequencer1.version = self.seqCount()
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self.sequencer1.dcache = self.L1D1cache
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self.sequencer1.ruby_system = ruby_system
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self.sequencer1.coreid = 1
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self.sequencer1.is_cpu_sequencer = True
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# Defines icache/dcache hit latency
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self.mandatory_queue_latency = 2
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self.issue_latency = options.cpu_to_dir_latency
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self.send_evictions = send_evicts(options)
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self.ruby_system = ruby_system
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if options.recycle_latency:
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self.recycle_latency = options.recycle_latency
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class L3Cache(RubyCache):
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assoc = 8
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dataArrayBanks = 256
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tagArrayBanks = 256
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def create(self, options, ruby_system, system):
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self.size = MemorySize(options.l3_size)
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self.size.value /= options.num_dirs
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self.dataArrayBanks /= options.num_dirs
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self.tagArrayBanks /= options.num_dirs
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self.dataArrayBanks /= options.num_dirs
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self.tagArrayBanks /= options.num_dirs
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self.dataAccessLatency = options.l3_data_latency
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self.tagAccessLatency = options.l3_tag_latency
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self.resourceStalls = options.no_resource_stalls
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self.replacement_policy = TreePLRURP()
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class L3Cntrl(L3Cache_Controller, CntrlBase):
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def create(self, options, ruby_system, system):
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self.version = self.versionCount()
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self.L3cache = L3Cache()
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self.L3cache.create(options, ruby_system, system)
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self.l3_response_latency = max(
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self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency
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)
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self.ruby_system = ruby_system
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if options.recycle_latency:
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self.recycle_latency = options.recycle_latency
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def connectWireBuffers(
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self,
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req_to_dir,
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resp_to_dir,
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l3_unblock_to_dir,
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req_to_l3,
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probe_to_l3,
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resp_to_l3,
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):
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self.reqToDir = req_to_dir
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self.respToDir = resp_to_dir
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self.l3UnblockToDir = l3_unblock_to_dir
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self.reqToL3 = req_to_l3
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self.probeToL3 = probe_to_l3
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self.respToL3 = resp_to_l3
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class DirCntrl(Directory_Controller, CntrlBase):
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def create(self, options, dir_ranges, ruby_system, system):
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self.version = self.versionCount()
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self.response_latency = 30
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self.addr_ranges = dir_ranges
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self.directory = RubyDirectoryMemory(
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block_size=ruby_system.block_size_bytes
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)
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self.L3CacheMemory = L3Cache()
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self.L3CacheMemory.create(options, ruby_system, system)
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self.l3_hit_latency = max(
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self.L3CacheMemory.dataAccessLatency,
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self.L3CacheMemory.tagAccessLatency,
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)
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self.number_of_TBEs = options.num_tbes
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self.ruby_system = ruby_system
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if options.recycle_latency:
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self.recycle_latency = options.recycle_latency
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self.CPUonly = True
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def connectWireBuffers(
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self,
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req_to_dir,
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resp_to_dir,
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l3_unblock_to_dir,
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req_to_l3,
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probe_to_l3,
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resp_to_l3,
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):
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self.reqToDir = req_to_dir
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self.respToDir = resp_to_dir
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self.l3UnblockToDir = l3_unblock_to_dir
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self.reqToL3 = req_to_l3
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self.probeToL3 = probe_to_l3
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self.respToL3 = resp_to_l3
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def define_options(parser):
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parser.add_argument("--num-subcaches", type=int, default=4)
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parser.add_argument("--l3-data-latency", type=int, default=20)
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parser.add_argument("--l3-tag-latency", type=int, default=15)
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parser.add_argument("--cpu-to-dir-latency", type=int, default=15)
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parser.add_argument(
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"--no-resource-stalls", action="store_false", default=True
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)
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parser.add_argument("--num-tbes", type=int, default=256)
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parser.add_argument("--l2-latency", type=int, default=50) # load to use
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def create_system(
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options, full_system, system, dma_devices, bootmem, ruby_system
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):
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if buildEnv["PROTOCOL"] != "MOESI_AMD_Base":
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panic("This script requires the MOESI_AMD_Base protocol.")
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to
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# be consistent with the NetDest list. Therefore the l1 controller
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# nodes must be listed before the directory nodes and directory nodes
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# before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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l3_cntrl_nodes = []
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dir_cntrl_nodes = []
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control_count = 0
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#
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# Must create the individual controllers before the network to ensure
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# the controller constructors are called before the network constructor
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#
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# This is the base crossbar that connects the L3s, Dirs, and cpu
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# Cluster
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mainCluster = Cluster(extBW=512, intBW=512) # 1 TB/s
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if options.numa_high_bit:
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numa_bit = options.numa_high_bit
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else:
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# if the numa_bit is not specified, set the directory bits as the
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# lowest bits above the block offset bits, and the numa_bit as the
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# highest of those directory bits
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dir_bits = int(math.log(options.num_dirs, 2))
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block_size_bits = int(math.log(options.cacheline_size, 2))
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numa_bit = block_size_bits + dir_bits - 1
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for i in range(options.num_dirs):
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dir_ranges = []
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for r in system.mem_ranges:
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addr_range = m5.objects.AddrRange(
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r.start,
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size=r.size(),
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intlvHighBit=numa_bit,
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intlvBits=dir_bits,
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intlvMatch=i,
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)
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dir_ranges.append(addr_range)
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dir_cntrl = DirCntrl(TCC_select_num_bits=0)
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dir_cntrl.create(options, dir_ranges, ruby_system, system)
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# Connect the Directory controller to the ruby network
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dir_cntrl.requestFromCores = MessageBuffer(ordered=True)
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dir_cntrl.requestFromCores.in_port = ruby_system.network.out_port
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dir_cntrl.responseFromCores = MessageBuffer()
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dir_cntrl.responseFromCores.in_port = ruby_system.network.out_port
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dir_cntrl.unblockFromCores = MessageBuffer()
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dir_cntrl.unblockFromCores.in_port = ruby_system.network.out_port
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dir_cntrl.probeToCore = MessageBuffer()
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dir_cntrl.probeToCore.out_port = ruby_system.network.in_port
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dir_cntrl.responseToCore = MessageBuffer()
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dir_cntrl.responseToCore.out_port = ruby_system.network.in_port
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dir_cntrl.triggerQueue = MessageBuffer(ordered=True)
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dir_cntrl.L3triggerQueue = MessageBuffer(ordered=True)
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dir_cntrl.requestToMemory = MessageBuffer()
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dir_cntrl.responseFromMemory = MessageBuffer()
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exec("system.dir_cntrl%d = dir_cntrl" % i)
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dir_cntrl_nodes.append(dir_cntrl)
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mainCluster.add(dir_cntrl)
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# Technically this config can support an odd number of cpus, but the top
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# level config files, such as the ruby_random_tester, will get confused if
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# the number of cpus does not equal the number of sequencers. Thus make
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# sure that an even number of cpus is specified.
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assert (options.num_cpus % 2) == 0
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# For an odd number of CPUs, still create the right number of controllers
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cpuCluster = Cluster(extBW=512, intBW=512) # 1 TB/s
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for i in range((options.num_cpus + 1) // 2):
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cp_cntrl = CPCntrl()
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cp_cntrl.create(options, ruby_system, system)
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exec("system.cp_cntrl%d = cp_cntrl" % i)
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
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# Connect the CP controllers and the network
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cp_cntrl.requestFromCore = MessageBuffer()
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cp_cntrl.requestFromCore.out_port = ruby_system.network.in_port
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cp_cntrl.responseFromCore = MessageBuffer()
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cp_cntrl.responseFromCore.out_port = ruby_system.network.in_port
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cp_cntrl.unblockFromCore = MessageBuffer()
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cp_cntrl.unblockFromCore.out_port = ruby_system.network.in_port
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cp_cntrl.probeToCore = MessageBuffer()
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cp_cntrl.probeToCore.in_port = ruby_system.network.out_port
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cp_cntrl.responseToCore = MessageBuffer()
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cp_cntrl.responseToCore.in_port = ruby_system.network.out_port
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cp_cntrl.mandatoryQueue = MessageBuffer()
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cp_cntrl.triggerQueue = MessageBuffer(ordered=True)
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cpuCluster.add(cp_cntrl)
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# Register CPUs and caches for each CorePair and directory (SE mode only)
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if not full_system:
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for i in range((options.num_cpus + 1) // 2):
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FileSystemConfig.register_cpu(
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physical_package_id=0,
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core_siblings=range(options.num_cpus),
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core_id=i * 2,
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thread_siblings=[],
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)
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FileSystemConfig.register_cpu(
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physical_package_id=0,
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core_siblings=range(options.num_cpus),
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core_id=i * 2 + 1,
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thread_siblings=[],
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)
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FileSystemConfig.register_cache(
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level=0,
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idu_type="Instruction",
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size=options.l1i_size,
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line_size=options.cacheline_size,
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assoc=options.l1i_assoc,
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cpus=[i * 2, i * 2 + 1],
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)
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FileSystemConfig.register_cache(
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level=0,
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idu_type="Data",
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size=options.l1d_size,
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line_size=options.cacheline_size,
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assoc=options.l1d_assoc,
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cpus=[i * 2],
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)
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FileSystemConfig.register_cache(
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level=0,
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idu_type="Data",
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size=options.l1d_size,
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line_size=options.cacheline_size,
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assoc=options.l1d_assoc,
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cpus=[i * 2 + 1],
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)
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FileSystemConfig.register_cache(
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level=1,
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idu_type="Unified",
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size=options.l2_size,
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line_size=options.cacheline_size,
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assoc=options.l2_assoc,
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cpus=[i * 2, i * 2 + 1],
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)
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for i in range(options.num_dirs):
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FileSystemConfig.register_cache(
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level=2,
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idu_type="Unified",
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size=options.l3_size,
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line_size=options.cacheline_size,
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assoc=options.l3_assoc,
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cpus=[n for n in range(options.num_cpus)],
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)
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# Assuming no DMA devices
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assert len(dma_devices) == 0
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# Add cpu/gpu clusters to main cluster
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mainCluster.add(cpuCluster)
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ruby_system.network.number_of_virtual_networks = 10
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return (cpu_sequencers, dir_cntrl_nodes, mainCluster)
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