4f4a710457
With recent changes to the memory system, a port cannot be assigned a peer port twice. While making use of the Ruby memory system in FS mode, DMA ports were assigned peer twice, once for the classic memory system and once for the Ruby memory system. This patch removes this double assignment of peer ports.
83 lines
3.3 KiB
Python
83 lines
3.3 KiB
Python
# Copyright (c) 2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.params import *
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from m5.proxy import *
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from Device import IsaFake
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from Pci import PciConfigAll
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from Platform import Platform
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from SouthBridge import SouthBridge
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from Terminal import Terminal
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from Uart import Uart8250
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def x86IOAddress(port):
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IO_address_space_base = 0x8000000000000000
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return IO_address_space_base + port;
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class Pc(Platform):
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type = 'Pc'
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system = Param.System(Parent.any, "system")
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pciconfig = PciConfigAll()
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south_bridge = SouthBridge()
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# "Non-existant" port used for timing purposes by the linux kernel
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i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
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# Ports behind the pci config and data regsiters. These don't do anything,
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# but the linux kernel fiddles with them anway.
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behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
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# Serial port and terminal
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terminal = Terminal()
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com_1 = Uart8250()
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com_1.pio_addr = x86IOAddress(0x3f8)
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com_1.terminal = terminal
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# Devices to catch access to non-existant serial ports.
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fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8)
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fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8)
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fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8)
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# A device to catch accesses to the non-existant floppy controller.
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fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
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def attachIO(self, bus, dma_ports = []):
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self.south_bridge.attachIO(bus, dma_ports)
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self.i_dont_exist.pio = bus.master
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self.behind_pci.pio = bus.master
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self.com_1.pio = bus.master
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self.fake_com_2.pio = bus.master
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self.fake_com_3.pio = bus.master
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self.fake_com_4.pio = bus.master
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self.fake_floppy.pio = bus.master
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self.pciconfig.pio = bus.default
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bus.use_default_range = True
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