Mitch Hayenga 976f27487b cpu: Change writeback modeling for outstanding instructions ...

As highlighed on the mailing list gem5's writeback modeling can impact
performance.  This patch removes the limitation on maximum outstanding issued
instructions, however the number that can writeback in a single cycle is still
respected in instToCommit().

2014-09-03 07:42:33 -04:00

..

Benchmarks.py

configs: add run scripts for ics/gb versions of android and bbench

2012-06-11 11:07:42 -04:00

CacheConfig.py

config: Update script to set cache line size on system

2013-07-18 08:31:19 -04:00

Caches.py

config: Update script to set cache line size on system

2013-07-18 08:31:19 -04:00

cpu2000.py

arm: Add support for ARMv8 (AArch64 & AArch32)

2014-01-24 15:29:34 -06:00

CpuConfig.py

cpu: `Minor' in-order CPU model

2014-07-23 16:09:04 -05:00

FSConfig.py

config: remove unecessary assignment of etherlink interfaces

2014-05-15 13:26:31 -04:00

MemConfig.py

mem: Rename SimpleDRAM to a more suitable DRAMCtrl

2014-03-23 11:12:12 -04:00

O3_ARM_v7a.py

cpu: Change writeback modeling for outstanding instructions

2014-09-03 07:42:33 -04:00

Options.py

config: add num-work-ids command line option

2014-04-10 13:43:33 -05:00

Simulation.py

config: add num-work-ids command line option

2014-04-10 13:43:33 -05:00

SysPaths.py

make rcS files read from the m5 source directory, not /dist.

2006-11-08 14:10:25 -05:00