6b4a1020be
Add support for MI200-like device. This includes adding PCI IDs and new MMIOs for the device, a different MAP_PROCESS packet, and a different calculation for the number of VGPRs. Change-Id: I0fb7b3ad928826beaa5386d52a94ba504369cb0d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70317 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
568 lines
13 KiB
C++
568 lines
13 KiB
C++
/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __DEV_AMDGPU_PM4_DEFINES_H__
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#define __DEV_AMDGPU_PM4_DEFINES_H__
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#include <cstdlib>
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#include <iostream>
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#include <vector>
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#include "base/types.hh"
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namespace gem5
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{
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/**
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* PM4 opcodes. Taken from linux tree from the following locations:
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* https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
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* drivers/gpu/drm/amd/amdkfd/kfd_pm4_opcodes.h
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* https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
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* drivers/gpu/drm/amd/amdgpu/soc15d.h
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*/
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enum it_opcode_type
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{
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IT_NOP = 0x10,
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IT_WRITE_DATA = 0x37,
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IT_WAIT_REG_MEM = 0x3C,
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IT_INDIRECT_BUFFER = 0x3F,
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IT_RELEASE_MEM = 0x49,
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IT_SET_UCONFIG_REG = 0x79,
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IT_SWITCH_BUFFER = 0x8B,
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IT_INVALIDATE_TLBS = 0x98,
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IT_MAP_PROCESS = 0xA1,
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IT_MAP_QUEUES = 0xA2,
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IT_UNMAP_QUEUES = 0xA3,
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IT_QUERY_STATUS = 0xA4,
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IT_RUN_LIST = 0xA5,
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};
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/**
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* Value from vega10/pm4_header.h.
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*/
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#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
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/**
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* PM4 packets
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*/
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typedef struct GEM5_PACKED
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{
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union
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{
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struct
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{
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uint16_t predicated : 1;
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uint16_t shader : 1;
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uint16_t reserved : 6;
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uint16_t opcode : 8;
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uint16_t count : 14;
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uint16_t type : 2;
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};
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uint32_t ordinal;
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};
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} PM4Header;
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static_assert(sizeof(PM4Header) == 4);
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typedef struct GEM5_PACKED
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{
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uint32_t reserved1 : 8;
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uint32_t destSel : 4;
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uint32_t reserved2 : 4;
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uint32_t addrIncr : 1;
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uint32_t reserved3 : 2;
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uint32_t resume : 1;
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uint32_t writeConfirm : 1;
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uint32_t reserved4 : 4;
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uint32_t cachePolicy : 2;
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uint32_t reserved5 : 5;
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union
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{
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struct
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{
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uint32_t destAddrLo;
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uint32_t destAddrHi;
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};
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uint64_t destAddr;
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};
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uint32_t data;
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} PM4WriteData;
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static_assert(sizeof(PM4WriteData) == 16);
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typedef struct GEM5_PACKED
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{
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uint32_t reserved1 : 4;
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uint32_t queueSel : 2;
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uint32_t reserved2 : 2;
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uint32_t vmid : 4;
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uint32_t reserved3 : 1;
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uint32_t queueSlot : 3;
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uint32_t pipe : 2;
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uint32_t me : 1;
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uint32_t reserved6 : 2;
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uint32_t queueType : 3;
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uint32_t allocFormat : 2;
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uint32_t engineSel : 3;
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uint32_t numQueues : 3;
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uint32_t reserved4 : 1;
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uint32_t checkDisable : 1;
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uint32_t doorbellOffset : 26;
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uint32_t reserved5 : 4;
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union
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{
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struct
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{
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uint32_t mqdAddrLo : 32;
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uint32_t mqdAddrHi : 32;
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};
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uint64_t mqdAddr;
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};
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union
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{
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struct
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{
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uint32_t wptrAddrLo : 32;
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uint32_t wptrAddrHi : 32;
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};
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uint64_t wptrAddr;
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};
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} PM4MapQueues;
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static_assert(sizeof(PM4MapQueues) == 24);
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typedef struct GEM5_PACKED
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{
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uint32_t action : 2;
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uint32_t reserved : 2;
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uint32_t queueSel : 2;
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uint32_t reserved1 : 20;
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uint32_t engineSel : 3;
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uint32_t numQueues : 3;
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union
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{
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struct
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{
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uint32_t pasid : 16;
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uint32_t reserved2 : 16;
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};
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struct
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{
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uint32_t reserved3 : 2;
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uint32_t doorbellOffset0 : 26;
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uint32_t reserved4 : 4;
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};
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};
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uint32_t reserved5 : 2;
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uint32_t doorbellOffset1 : 26;
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uint32_t reserved6 : 4;
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uint32_t reserved7 : 2;
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uint32_t doorbellOffset2 : 26;
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uint32_t reserved8 : 4;
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uint32_t reserved9 : 2;
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uint32_t doorbellOffset3 : 26;
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uint32_t reserved10 : 4;
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} PM4UnmapQueues;
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static_assert(sizeof(PM4UnmapQueues) == 20);
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typedef struct GEM5_PACKED
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{
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uint32_t vmidMask : 16;
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uint32_t unmapLatency : 8;
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uint32_t reserved : 5;
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uint32_t queueType : 3;
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union
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{
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struct
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{
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uint32_t queueMaskLo;
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uint32_t queueMaskHi;
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};
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uint64_t queueMask;
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};
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union
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{
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struct
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{
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uint32_t gwsMaskLo;
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uint32_t gwsMaskHi;
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};
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uint64_t gwsMask;
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};
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uint16_t oacMask;
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uint16_t reserved1;
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uint32_t gdsHeapBase : 6;
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uint32_t reserved2 : 5;
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uint32_t gdsHeapSize : 6;
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uint32_t reserved3 : 15;
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} PM4SetResources;
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static_assert(sizeof(PM4SetResources) == 28);
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typedef struct GEM5_PACKED
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{
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uint32_t pasid : 16;
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uint32_t reserved0 : 8;
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uint32_t diq : 1;
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uint32_t processQuantum : 7;
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union
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{
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struct
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{
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uint32_t ptBaseLo;
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uint32_t ptBaseHi;
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};
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uint64_t ptBase;
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};
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uint32_t shMemBases;
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uint32_t shMemConfig;
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uint32_t reserved1;
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uint32_t reserved2;
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uint32_t reserved3;
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uint32_t reserved4;
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uint32_t reserved5;
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union
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{
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struct
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{
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uint32_t gdsAddrLo;
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uint32_t gdsAddrHi;
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};
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uint64_t gdsAddr;
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};
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uint32_t numGws : 6;
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uint32_t reserved7 : 2;
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uint32_t numOac : 4;
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uint32_t reserved8 : 4;
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uint32_t gdsSize : 6;
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uint32_t numQueues : 10;
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union
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{
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struct
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{
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uint32_t completionSignalLo;
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uint32_t completionSignalHi;
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};
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uint64_t completionSignal;
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};
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} PM4MapProcess;
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static_assert(sizeof(PM4MapProcess) == 60);
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typedef struct GEM5_PACKED
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{
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uint32_t pasid : 16;
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uint32_t reserved0 : 8;
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uint32_t diq : 1;
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uint32_t processQuantum : 7;
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union
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{
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struct
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{
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uint32_t ptBaseLo;
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uint32_t ptBaseHi;
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};
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uint64_t ptBase;
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};
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uint32_t shMemBases;
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uint32_t shMemConfig;
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uint32_t sqShaderTbaLo;
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uint32_t sqShaderTbaHi;
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uint32_t sqShaderTmaLo;
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uint32_t sqShaderTmaHi;
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uint32_t reserved1;
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union
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{
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struct
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{
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uint32_t gdsAddrLo;
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uint32_t gdsAddrHi;
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};
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uint64_t gdsAddr;
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};
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union
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{
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struct
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{
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uint32_t numGws : 7;
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uint32_t sdma_enable : 1;
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uint32_t numOac : 4;
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uint32_t reserved3 : 4;
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uint32_t gdsSize : 6;
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uint32_t numQueues : 10;
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};
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uint32_t ordinal14;
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};
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uint32_t spiGdbgPerVmidCntl;
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uint32_t tcpWatchCntl[4];
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union
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{
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struct
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{
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uint32_t completionSignalLo;
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uint32_t completionSignalHi;
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};
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uint64_t completionSignal;
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};
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} PM4MapProcessMI200;
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static_assert(sizeof(PM4MapProcessMI200) == 80);
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typedef struct GEM5_PACKED
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{
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uint32_t function : 4;
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uint32_t memSpace : 2;
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uint32_t operation : 2;
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uint32_t reserved1 : 24;
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union
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{
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struct
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{
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uint32_t regAddr1 : 18;
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uint32_t reserved2 : 14;
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};
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uint32_t memAddrLo;
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};
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union
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{
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struct
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{
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uint32_t regAddr2 : 18;
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uint32_t reserved3 : 14;
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};
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uint32_t memAddrHi;
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};
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uint32_t reference;
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uint32_t mask;
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uint32_t pollInterval;
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} PM4WaitRegMem;
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static_assert(sizeof(PM4WaitRegMem) == 24);
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typedef struct GEM5_PACKED
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{
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uint32_t regOffset : 16;
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uint32_t reserved : 16;
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uint32_t regData;
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} PM4SetUConfig;
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static_assert(sizeof(PM4SetUConfig) == 8);
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typedef struct GEM5_PACKED
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{
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union
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{
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struct
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{
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uint32_t ibBaseLo;
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uint32_t ibBaseHi;
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};
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uint64_t ibBase;
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};
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uint32_t ibSize : 20;
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uint32_t chain : 1;
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uint32_t poll : 1;
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uint32_t reserved0 : 1;
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uint32_t valid: 1;
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uint32_t vmid : 4;
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uint32_t cachePolicy : 2;
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uint32_t reserved1 : 1;
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uint32_t priv : 1;
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} PM4IndirectBuf;
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static_assert(sizeof(PM4IndirectBuf) == 12);
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typedef struct GEM5_PACKED
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{
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union
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{
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struct
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{
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uint32_t tmz : 1;
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uint32_t reserved : 31;
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};
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uint32_t dummy;
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};
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} PM4SwitchBuf;
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static_assert(sizeof(PM4SwitchBuf) == 4);
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typedef struct GEM5_PACKED
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{
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union
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{
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struct
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{
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uint32_t ibBaseLo;
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uint32_t ibBaseHi;
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};
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uint64_t ibBase;
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};
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uint32_t ibSize : 20;
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uint32_t chain : 1;
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uint32_t ena : 1;
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uint32_t reserved1 : 2;
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uint32_t vmid : 4;
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uint32_t cachePolicy : 2;
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uint32_t preResume : 1;
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uint32_t priv : 1;
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} PM4IndirectBufConst;
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static_assert(sizeof(PM4IndirectBufConst) == 12);
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typedef struct GEM5_PACKED
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{
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uint32_t tmz : 1;
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uint32_t reserved : 27;
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uint32_t command : 4;
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} PM4FrameCtrl;
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static_assert(sizeof(PM4FrameCtrl) == 4);
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typedef struct GEM5_PACKED
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{
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uint32_t event : 6;
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uint32_t reserved0 : 2;
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uint32_t eventIdx : 4;
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uint32_t l1Volatile : 1;
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uint32_t l2Volatile : 1;
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uint32_t reserved1 : 1;
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uint32_t l2WB : 1;
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uint32_t l1Inv : 1;
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uint32_t l2Inv : 1;
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uint32_t reserved2 : 1;
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uint32_t l2NC : 1;
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uint32_t l2WC : 1;
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uint32_t l2Meta : 1;
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uint32_t reserved3 : 3;
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uint32_t cachePolicy : 2;
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uint32_t reserved4 : 1;
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uint32_t execute : 1;
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uint32_t reserved5 : 3;
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uint32_t reserved6 : 16;
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uint32_t destSelect : 2;
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uint32_t reserved7 : 6;
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uint32_t intSelect : 3;
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uint32_t reserved8 : 2;
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uint32_t dataSelect : 3;
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union
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{
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struct
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{
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uint32_t addrLo;
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uint32_t addrHi;
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};
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uint64_t addr;
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};
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union
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{
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struct
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{
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union
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{
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struct
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{
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uint32_t dwOffset : 16;
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uint32_t numDws : 16;
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};
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uint32_t dataLo : 32;
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};
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uint32_t dataHi;
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};
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uint64_t data;
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};
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uint32_t intCtxId;
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} PM4ReleaseMem;
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static_assert(sizeof(PM4ReleaseMem) == 28);
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typedef struct GEM5_PACKED
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{
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uint32_t offset : 16;
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uint32_t reserved : 16;
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uint32_t data;
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} PM4SetUconfigReg;
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static_assert(sizeof(PM4SetUconfigReg) == 8);
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typedef struct GEM5_PACKED
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{
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union
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{
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struct
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{
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uint32_t ibBaseLo;
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uint32_t ibBaseHi;
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};
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uint64_t ibBase;
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};
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uint32_t ibSize : 20;
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uint32_t chain : 1;
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uint32_t offleadPolling : 1;
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uint32_t reserved1 : 1;
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uint32_t valid : 1;
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uint32_t processCnt : 4;
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uint32_t reserved2 : 4;
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} PM4RunList;
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static_assert(sizeof(PM4RunList) == 12);
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typedef struct GEM5_PACKED
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{
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uint32_t contextId : 28;
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uint32_t interruptSel : 2;
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uint32_t command : 2;
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union
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{
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struct
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{
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uint32_t pasid : 16;
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uint32_t reserved0 : 16;
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};
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struct
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{
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uint32_t reserved1 : 2;
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uint32_t doorbellOffset : 26;
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uint32_t engineSel : 3;
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uint32_t reserved2 : 1;
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};
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};
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union
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{
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struct
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{
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uint32_t addrLo;
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uint32_t addrHi;
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};
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uint64_t addr;
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};
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union
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{
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struct
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{
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uint32_t dataLo;
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uint32_t dataHi;
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};
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uint64_t data;
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};
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} PM4QueryStatus;
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static_assert(sizeof(PM4QueryStatus) == 24);
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} // namespace gem5
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#endif // __DEV_AMDGPU_PM4_DEFINES_HH__
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