2922f763e1
The systemc dir was not included in this fix.
First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:
grep -nrE --exclude-dir=systemc \
"^ *struct [A-Za-z].* {$" src/
Then the following commands were run to replace:
<indent level>struct X ... {
by:
<indent level>struct X ...
<indent level>{
Level 0:
grep -nrl --exclude-dir=systemc
"^struct [A-Za-z].* {$" src/ | \
xargs sed -Ei \
's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'
Level 1:
grep -nrl --exclude-dir=systemc \
"^ struct [A-Za-z].* {$" src/ | \
xargs sed -Ei \
's/^ struct ([A-Za-z].*) \{$/ struct \1\n \{/g'
and so on.
Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
103 lines
3.7 KiB
C++
103 lines
3.7 KiB
C++
/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_PRED_INDIRECT_HH__
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#define __CPU_PRED_INDIRECT_HH__
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#include <deque>
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#include "config/the_isa.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/pred/indirect.hh"
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#include "params/SimpleIndirectPredictor.hh"
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class SimpleIndirectPredictor : public IndirectPredictor
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{
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public:
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SimpleIndirectPredictor(const SimpleIndirectPredictorParams ¶ms);
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bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
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void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
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ThreadID tid);
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void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
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void squash(InstSeqNum seq_num, ThreadID tid);
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void recordTarget(InstSeqNum seq_num, void * indirect_history,
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const TheISA::PCState& target, ThreadID tid);
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void genIndirectInfo(ThreadID tid, void* & indirect_history);
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void updateDirectionInfo(ThreadID tid, bool actually_taken);
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void deleteIndirectInfo(ThreadID tid, void * indirect_history);
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void changeDirectionPrediction(ThreadID tid, void * indirect_history,
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bool actually_taken);
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private:
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const bool hashGHR;
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const bool hashTargets;
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const unsigned numSets;
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const unsigned numWays;
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const unsigned tagBits;
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const unsigned pathLength;
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const unsigned instShift;
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const unsigned ghrNumBits;
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const unsigned ghrMask;
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struct IPredEntry
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{
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IPredEntry() : tag(0), target(0) { }
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Addr tag;
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TheISA::PCState target;
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};
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std::vector<std::vector<IPredEntry> > targetCache;
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Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid);
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Addr getTag(Addr br_addr);
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struct HistoryEntry
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{
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HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num)
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: pcAddr(br_addr), targetAddr(tgt_addr), seqNum(seq_num) { }
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Addr pcAddr;
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Addr targetAddr;
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InstSeqNum seqNum;
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};
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struct ThreadInfo
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{
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ThreadInfo() : headHistEntry(0), ghr(0) { }
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std::deque<HistoryEntry> pathHist;
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unsigned headHistEntry;
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unsigned ghr;
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};
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std::vector<ThreadInfo> threadInfo;
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};
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#endif // __CPU_PRED_INDIRECT_HH__
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