As part of recent decisions regarding namespace naming conventions, all namespaces will be changed to snake case. ::Enums became ::enums. Change-Id: I39b5fb48817ad16abbac92f6254284b37fc90c40 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45420 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
126 lines
3.6 KiB
C++
126 lines
3.6 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_X86_I8259_HH__
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#define __DEV_X86_I8259_HH__
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#include "dev/intpin.hh"
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#include "dev/io_device.hh"
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#include "enums/X86I8259CascadeMode.hh"
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#include "params/I8259.hh"
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namespace X86ISA
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{
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class I8259 : public BasicPioDevice
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{
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protected:
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static const int NumLines = 8;
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bool pinStates[NumLines];
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void init() override;
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Tick latency;
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std::vector<IntSourcePin<I8259> *> output;
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std::vector<IntSinkPin<I8259> *> inputs;
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enums::X86I8259CascadeMode mode;
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I8259 *slave;
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// Interrupt Request Register
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uint8_t IRR;
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// In Service Register
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uint8_t ISR;
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// Interrupt Mask Register
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uint8_t IMR;
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// The higher order bits of the vector to return
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uint8_t vectorOffset;
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bool cascadeMode;
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// A bit vector of lines with responders attached, or the
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// responder id, depending
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// on if this is a requestor or responder PIC.
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uint8_t cascadeBits;
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bool edgeTriggered;
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bool readIRR;
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// State machine information for reading in initialization control words.
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bool expectICW4;
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int initControlWord;
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// Whether or not the PIC is in auto EOI mode.
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bool autoEOI;
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void requestInterrupt(int line);
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void handleEOI(int line);
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public:
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using Params = I8259Params;
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I8259(const Params &p);
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Port &
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getPort(const std::string &if_name, PortID idx=InvalidPortID) override
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{
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if (if_name == "inputs")
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return *inputs.at(idx);
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else if (if_name == "output")
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return *output.at(idx);
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else
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return BasicPioDevice::getPort(if_name, idx);
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}
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Tick read(PacketPtr pkt) override;
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Tick write(PacketPtr pkt) override;
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void
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maskAll()
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{
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IMR = 0xFF;
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}
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void
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unmaskAll()
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{
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IMR = 0x00;
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}
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void signalInterrupt(int line);
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void raiseInterruptPin(int number);
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void lowerInterruptPin(int number);
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int getVector();
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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};
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} // namespace X86ISA
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#endif //__DEV_X86_I8259_HH__
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