0f024be0ca
The supported registers are essentially the same as before this patch, but it is now trivial to make new registers visible in future commits. Change-Id: Id15b7aeccca824c342e49a626d2877179474f3d4 Reviewed-on: https://gem5-review.googlesource.com/c/15138 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
132 lines
4.4 KiB
C++
132 lines
4.4 KiB
C++
/*
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* Copyright 2015 LabWare
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* Copyright 2014 Google, Inc.
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* Copyright (c) 2013, 2016, 2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Stephen Hines
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* Boris Shingarov
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*/
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#ifndef __ARCH_ARM_REMOTE_GDB_HH__
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#define __ARCH_ARM_REMOTE_GDB_HH__
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#include <algorithm>
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#include "arch/arm/registers.hh"
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#include "arch/arm/utility.hh"
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#include "base/compiler.hh"
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#include "base/remote_gdb.hh"
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class System;
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class ThreadContext;
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namespace ArmISA
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{
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class RemoteGDB : public BaseRemoteGDB
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{
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protected:
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bool acc(Addr addr, size_t len);
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class AArch32GdbRegCache : public BaseGdbRegCache
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{
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using BaseGdbRegCache::BaseGdbRegCache;
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private:
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struct {
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uint32_t gpr[16];
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uint32_t cpsr;
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uint64_t fpr[32];
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uint32_t fpscr;
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} M5_ATTR_PACKED r;
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public:
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char *data() const { return (char *)&r; }
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size_t size() const { return sizeof(r); }
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void getRegs(ThreadContext*);
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void setRegs(ThreadContext*) const;
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const std::string
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name() const
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{
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return gdb->name() + ".AArch32GdbRegCache";
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}
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};
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class AArch64GdbRegCache : public BaseGdbRegCache
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{
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using BaseGdbRegCache::BaseGdbRegCache;
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private:
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struct {
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uint64_t x[31];
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uint64_t spx;
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uint64_t pc;
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uint32_t cpsr;
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VecElem v[NumVecV8ArchRegs * NumVecElemPerVecReg];
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uint32_t fpsr;
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uint32_t fpcr;
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} M5_ATTR_PACKED r;
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public:
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char *data() const { return (char *)&r; }
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size_t size() const { return sizeof(r); }
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void getRegs(ThreadContext*);
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void setRegs(ThreadContext*) const;
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const std::string
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name() const
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{
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return gdb->name() + ".AArch64GdbRegCache";
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}
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};
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AArch32GdbRegCache regCache32;
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AArch64GdbRegCache regCache64;
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public:
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RemoteGDB(System *_system, ThreadContext *tc, int _port);
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BaseGdbRegCache *gdbRegs();
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std::vector<std::string>
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availableFeatures() const
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{
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return {"qXfer:features:read+"};
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};
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bool getXferFeaturesRead(const std::string &annex, std::string &output);
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};
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} // namespace ArmISA
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#endif /* __ARCH_ARM_REMOTE_GDB_H__ */
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