Korey Sewell d5d4e47f76 sparc: init. cache state in TLB ...

valgrind complains and its a potential source of instability, so go ahead
and set it to 0 to start

2011-06-19 21:43:35 -04:00

..

alpha

copyright: clean up copyright blocks

2011-06-02 14:36:35 -07:00

arm

cpus/isa: add a != operator for pcstate

2011-06-19 21:43:33 -04:00

generic

cpus/isa: add a != operator for pcstate

2011-06-19 21:43:33 -04:00

mips

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00

noisa

SCons: Support building without an ISA

2010-11-19 18:00:39 -06:00

power

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00

sparc

sparc: init. cache state in TLB

2011-06-19 21:43:35 -04:00

x86

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00

isa_parser.py

ISA parser: Loosen the regular expressions matching filenames.

2011-06-07 00:46:54 -07:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00