Sandipan Das 4b948e64bd arch-power: Refactor shift instructions ...

This changes the format for integer shift instructions
such that the computation of the carry bit is implicitly
handled rather than including it in the definition of an
instruction.

Change-Id: Ib916597287efd51b2c9e8781209a8019f2fc38e8
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40924
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-06-29 14:00:38 +00:00

..

arch

arch-power: Refactor shift instructions

2021-06-29 14:00:38 +00:00

base

base: Improved less-than operator for AddrRange

2021-06-29 02:46:08 +00:00

cpu

cpu-o3: add more DPRINTF for when cache is blocked

2021-06-24 07:37:35 +00:00

dev

dev,sim: Fix compiler not finding specialized byte_swap

2021-06-28 20:25:07 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

kern

misc: Clean up ISA switching header includes.

2021-05-28 23:41:03 +00:00

learning_gem5

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

mem

mem-cache: Add MSHR debuging information

2021-06-29 07:06:30 +00:00

proto

python,scons: Move readCommand and compareVersions into site_scons.

2021-05-10 23:33:22 +00:00

python

python,scons,mem-ruby: Tag origin of generated files

2021-06-28 20:25:07 +00:00

sim

sim: Add serialization for file descriptor array

2021-06-29 07:06:05 +00:00

systemc

systemc: Set verify.py shebang to python3

2021-06-23 17:31:27 +00:00

Doxyfile

misc: Revert version info back to develop

2021-06-24 18:17:16 +00:00

SConscript

python,scons,mem-ruby: Tag origin of generated files

2021-06-28 20:25:07 +00:00