Mitch Hayenga 4acd4a2055 mem: Fix bug relating to writebacks and prefetches ...

Previously the code commented about an unhandled case where it might be
possible for a writeback to arrive after a prefetch was generated but
before it was sent to the memory system.  I hit that case.  Luckily
the prefetchSquash() logic already in the code handles dropping prefetch
request in certian circumstances.

2014-12-23 09:31:18 -05:00

..

arch

arm: Add stats to table walker

2014-12-23 09:31:18 -05:00

base

misc: Generalize GDB single stepping.

2014-12-05 22:37:03 -08:00

cpu

Let other objects set up memory like regions in a KVM VM.

2014-12-09 21:53:44 -08:00

dev

arm: Add stats to table walker

2014-12-23 09:31:18 -05:00

doc

cpu: `Minor' in-order CPU model

2014-07-23 16:09:04 -05:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

kern

misc: Move AddrRangeList from port.hh to addr_range.hh

2014-10-16 05:49:59 -04:00

mem

mem: Fix bug relating to writebacks and prefetches

2014-12-23 09:31:18 -05:00

proto

mem: change the namespace Message to ProtoMessage

2014-09-01 16:55:46 -05:00

python

scons: Ensure dictionary iteration is sorted by key

2014-12-02 06:08:22 -05:00

sim

misc: Another round of static analysis fixups

2014-11-24 09:03:38 -05:00

unittest

unittest: Fix build errors

2014-01-30 12:21:58 -06:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

scons: Ensure dictionary iteration is sorted by key

2014-12-02 06:08:22 -05:00