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49507982685b4e807e612ff176fb67901415a2ce
gem5/src/arch
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Gabe Black 4950798268 X86: Implement tlb invalidation and make it happen some of the times it should.
--HG--
extra : convert_revision : 376516d33cd539fa526c834ef2b2c33069af3040
2007-11-12 14:39:07 -08:00
..
alpha
Alpha: Fix a long standing bug where all code ran as PAL code in FS.
2007-11-08 23:50:10 -08:00
mips
ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs.
2007-11-08 18:51:50 -08:00
sparc
SPARC: Force %g1 to be zero on process startup even though it normally already should be.
2007-11-11 17:23:22 -08:00
x86
X86: Implement tlb invalidation and make it happen some of the times it should.
2007-11-12 14:39:07 -08:00
isa_parser.py
ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs.
2007-11-08 18:51:50 -08:00
isa_specific.hh
Add build hooks for x86.
2007-03-03 16:01:48 +00:00
micro_asm_test.py
Add a second section to make sure the ROM is extended properly.
2007-05-31 22:21:21 +00:00
micro_asm.py
Microassembler: Pass the actual mnemonic used to the macroop add_micro function
2007-08-31 22:26:02 -07:00
SConscript
ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs.
2007-11-08 18:51:50 -08:00
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