This change separates the pipeline stage interfaces for the GPU's compute unit into their own classes with a well-defined interface. This helps to create a cleaner interface for users to extend the CU pipeline's capabilities and also helps consolidate all the pipeline communication code in one place in the source. Change-Id: I569d52bce84dc1b9fbf8f0f96d53a81a2b6773c6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29972 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
155 lines
4.5 KiB
C++
155 lines
4.5 KiB
C++
/*
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* Copyright (c) 2018 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Anthony Gutierrez
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*/
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#include "gpu-compute/comm.hh"
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#include <cassert>
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#include "gpu-compute/wavefront.hh"
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#include "params/ComputeUnit.hh"
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/**
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* Scoreboard/Schedule stage interface.
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*/
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ScoreboardCheckToSchedule::ScoreboardCheckToSchedule(const ComputeUnitParams
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*p)
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{
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int num_func_units = p->num_SIMDs + p->num_scalar_cores
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+ p->num_global_mem_pipes + p->num_shared_mem_pipes
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+ p->num_scalar_mem_pipes;
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_readyWFs.resize(num_func_units);
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for (auto &func_unit_wf_list : _readyWFs) {
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func_unit_wf_list.reserve(p->n_wf);
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}
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}
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void
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ScoreboardCheckToSchedule::reset()
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{
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for (auto &func_unit_wf_list : _readyWFs) {
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func_unit_wf_list.resize(0);
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}
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}
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void
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ScoreboardCheckToSchedule::markWFReady(Wavefront *wf, int func_unit_id)
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{
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_readyWFs[func_unit_id].push_back(wf);
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}
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int
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ScoreboardCheckToSchedule::numReadyLists() const
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{
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return _readyWFs.size();
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}
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std::vector<Wavefront*>&
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ScoreboardCheckToSchedule::readyWFs(int func_unit_id)
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{
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return _readyWFs[func_unit_id];
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}
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/**
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* Delete all wavefronts that have been marked as ready at scoreboard stage
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* but are found to have empty instruction buffers at schedule stage.
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*/
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void
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ScoreboardCheckToSchedule::updateReadyList(int func_unit_id)
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{
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std::vector<Wavefront*> &func_unit_wf_list = _readyWFs[func_unit_id];
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for (auto it = func_unit_wf_list.begin(); it != func_unit_wf_list.end();) {
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if ((*it)->instructionBuffer.empty()) {
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it = func_unit_wf_list.erase(it);
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} else {
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++it;
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}
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}
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}
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/**
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* Schedule/Execute stage interface.
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*/
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ScheduleToExecute::ScheduleToExecute(const ComputeUnitParams *p)
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{
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int num_func_units = p->num_SIMDs + p->num_scalar_cores
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+ p->num_global_mem_pipes + p->num_shared_mem_pipes
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+ p->num_scalar_mem_pipes;
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_readyInsts.resize(num_func_units, nullptr);
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_dispatchStatus.resize(num_func_units, EMPTY);
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}
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void
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ScheduleToExecute::reset()
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{
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for (auto &func_unit_ready_inst : _readyInsts) {
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func_unit_ready_inst = nullptr;
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}
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for (auto &func_unit_status : _dispatchStatus) {
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func_unit_status = EMPTY;
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}
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}
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GPUDynInstPtr&
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ScheduleToExecute::readyInst(int func_unit_id)
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{
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return _readyInsts[func_unit_id];
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}
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void
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ScheduleToExecute::dispatchTransition(const GPUDynInstPtr &gpu_dyn_inst,
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int func_unit_id,
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DISPATCH_STATUS disp_status)
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{
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_readyInsts[func_unit_id] = gpu_dyn_inst;
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_dispatchStatus[func_unit_id] = disp_status;
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}
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void
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ScheduleToExecute::dispatchTransition(int func_unit_id,
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DISPATCH_STATUS disp_status)
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{
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_readyInsts[func_unit_id] = nullptr;
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_dispatchStatus[func_unit_id] = disp_status;
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}
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DISPATCH_STATUS
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ScheduleToExecute::dispatchStatus(int func_unit_id) const
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{
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return _dispatchStatus[func_unit_id];
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}
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