679ed0eec5
Change-Id: I3915f0ad673119b551dcc4c5cedec180a9b88735 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20702 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
315 lines
11 KiB
C++
315 lines
11 KiB
C++
/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "dev/x86/i8042.hh"
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#include "base/bitunion.hh"
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#include "debug/I8042.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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/**
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* Note: For details on the implementation see
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* https://wiki.osdev.org/%228042%22_PS/2_Controller
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*/
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// The 8042 has a whopping 32 bytes of internal RAM.
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const uint8_t RamSize = 32;
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const uint8_t NumOutputBits = 14;
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X86ISA::I8042::I8042(Params *p)
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: BasicPioDevice(p, 0), // pioSize arg is dummy value... not used
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latency(p->pio_latency),
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dataPort(p->data_port), commandPort(p->command_port),
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statusReg(0), commandByte(0), dataReg(0), lastCommand(NoCommand),
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mouse(p->mouse), keyboard(p->keyboard)
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{
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fatal_if(!mouse, "The i8042 model requires a mouse instance");
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fatal_if(!keyboard, "The i8042 model requires a keyboard instance");
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statusReg.passedSelfTest = 1;
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statusReg.commandLast = 1;
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statusReg.keyboardUnlocked = 1;
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commandByte.convertScanCodes = 1;
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commandByte.passedSelfTest = 1;
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commandByte.keyboardFullInt = 1;
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for (int i = 0; i < p->port_keyboard_int_pin_connection_count; i++) {
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keyboardIntPin.push_back(new IntSourcePin<I8042>(
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csprintf("%s.keyboard_int_pin[%d]", name(), i), i, this));
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}
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for (int i = 0; i < p->port_mouse_int_pin_connection_count; i++) {
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mouseIntPin.push_back(new IntSourcePin<I8042>(
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csprintf("%s.mouse_int_pin[%d]", name(), i), i, this));
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}
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}
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AddrRangeList
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X86ISA::I8042::getAddrRanges() const
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{
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AddrRangeList ranges;
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// TODO: Are these really supposed to be a single byte and not 4?
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ranges.push_back(RangeSize(dataPort, 1));
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ranges.push_back(RangeSize(commandPort, 1));
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return ranges;
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}
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void
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X86ISA::I8042::writeData(uint8_t newData, bool mouse)
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{
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DPRINTF(I8042, "Set data %#02x.\n", newData);
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dataReg = newData;
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statusReg.outputFull = 1;
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statusReg.mouseOutputFull = (mouse ? 1 : 0);
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if (!mouse && commandByte.keyboardFullInt) {
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DPRINTF(I8042, "Sending keyboard interrupt.\n");
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for (auto *wire: keyboardIntPin) {
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wire->raise();
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//This is a hack
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wire->lower();
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}
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} else if (mouse && commandByte.mouseFullInt) {
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DPRINTF(I8042, "Sending mouse interrupt.\n");
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for (auto *wire: mouseIntPin) {
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wire->raise();
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//This is a hack
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wire->lower();
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}
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}
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}
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uint8_t
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X86ISA::I8042::readDataOut()
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{
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uint8_t data = dataReg;
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statusReg.outputFull = 0;
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statusReg.mouseOutputFull = 0;
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if (keyboard->hostDataAvailable()) {
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writeData(keyboard->hostRead(), false);
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} else if (mouse->hostDataAvailable()) {
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writeData(mouse->hostRead(), true);
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}
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return data;
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}
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Tick
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X86ISA::I8042::read(PacketPtr pkt)
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{
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assert(pkt->getSize() == 1);
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Addr addr = pkt->getAddr();
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if (addr == dataPort) {
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uint8_t data = readDataOut();
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//DPRINTF(I8042, "Read from data port got %#02x.\n", data);
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pkt->setLE<uint8_t>(data);
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} else if (addr == commandPort) {
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//DPRINTF(I8042, "Read status as %#02x.\n", (uint8_t)statusReg);
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pkt->setLE<uint8_t>((uint8_t)statusReg);
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} else {
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panic("Read from unrecognized port %#x.\n", addr);
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}
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pkt->makeAtomicResponse();
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return latency;
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}
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Tick
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X86ISA::I8042::write(PacketPtr pkt)
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{
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assert(pkt->getSize() == 1);
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Addr addr = pkt->getAddr();
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uint8_t data = pkt->getLE<uint8_t>();
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if (addr == dataPort) {
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statusReg.commandLast = 0;
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switch (lastCommand) {
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case NoCommand:
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keyboard->hostWrite(data);
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if (keyboard->hostDataAvailable())
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writeData(keyboard->hostRead(), false);
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break;
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case WriteToMouse:
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mouse->hostWrite(data);
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if (mouse->hostDataAvailable())
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writeData(mouse->hostRead(), true);
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break;
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case WriteCommandByte:
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commandByte = data;
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DPRINTF(I8042, "Got data %#02x for \"Write "
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"command byte\" command.\n", data);
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statusReg.passedSelfTest = (uint8_t)commandByte.passedSelfTest;
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break;
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case WriteMouseOutputBuff:
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DPRINTF(I8042, "Got data %#02x for \"Write "
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"mouse output buffer\" command.\n", data);
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writeData(data, true);
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break;
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case WriteKeyboardOutputBuff:
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DPRINTF(I8042, "Got data %#02x for \"Write "
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"keyboad output buffer\" command.\n", data);
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writeData(data, false);
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break;
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case WriteOutputPort:
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DPRINTF(I8042, "Got data %#02x for \"Write "
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"output port\" command.\n", data);
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panic_if(bits(data, 0) != 1, "Reset bit should be 1");
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// Safe to ignore otherwise
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break;
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default:
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panic("Data written for unrecognized "
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"command %#02x\n", lastCommand);
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}
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lastCommand = NoCommand;
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} else if (addr == commandPort) {
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DPRINTF(I8042, "Got command %#02x.\n", data);
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statusReg.commandLast = 1;
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// These purposefully leave off the first byte of the controller RAM
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// so it can be handled specially.
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if (data > ReadControllerRamBase &&
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data < ReadControllerRamBase + RamSize) {
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panic("Attempted to use i8042 read controller RAM command to "
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"get byte %d.\n", data - ReadControllerRamBase);
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} else if (data > WriteControllerRamBase &&
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data < WriteControllerRamBase + RamSize) {
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panic("Attempted to use i8042 read controller RAM command to "
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"get byte %d.\n", data - ReadControllerRamBase);
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} else if (data >= PulseOutputBitBase &&
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data < PulseOutputBitBase + NumOutputBits) {
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panic("Attempted to use i8042 pulse output bit command to "
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"to pulse bit %d.\n", data - PulseOutputBitBase);
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}
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switch (data) {
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case GetCommandByte:
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DPRINTF(I8042, "Getting command byte.\n");
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writeData(commandByte);
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break;
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case WriteCommandByte:
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DPRINTF(I8042, "Setting command byte.\n");
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lastCommand = WriteCommandByte;
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break;
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case CheckForPassword:
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panic("i8042 \"Check for password\" command not implemented.\n");
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case LoadPassword:
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panic("i8042 \"Load password\" command not implemented.\n");
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case CheckPassword:
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panic("i8042 \"Check password\" command not implemented.\n");
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case DisableMouse:
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DPRINTF(I8042, "Disabling mouse at controller.\n");
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commandByte.disableMouse = 1;
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break;
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case EnableMouse:
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DPRINTF(I8042, "Enabling mouse at controller.\n");
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commandByte.disableMouse = 0;
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break;
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case TestMouse:
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panic("i8042 \"Test mouse\" command not implemented.\n");
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case SelfTest:
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panic("i8042 \"Self test\" command not implemented.\n");
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case InterfaceTest:
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panic("i8042 \"Interface test\" command not implemented.\n");
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case DiagnosticDump:
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panic("i8042 \"Diagnostic dump\" command not implemented.\n");
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case DisableKeyboard:
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DPRINTF(I8042, "Disabling keyboard at controller.\n");
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commandByte.disableKeyboard = 1;
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break;
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case EnableKeyboard:
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DPRINTF(I8042, "Enabling keyboard at controller.\n");
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commandByte.disableKeyboard = 0;
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break;
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case ReadInputPort:
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panic("i8042 \"Read input port\" command not implemented.\n");
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case ContinuousPollLow:
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panic("i8042 \"Continuous poll low\" command not implemented.\n");
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case ContinuousPollHigh:
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panic("i8042 \"Continuous poll high\" command not implemented.\n");
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case ReadOutputPort:
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panic("i8042 \"Read output port\" command not implemented.\n");
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case WriteOutputPort:
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lastCommand = WriteOutputPort;
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break;
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case WriteKeyboardOutputBuff:
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lastCommand = WriteKeyboardOutputBuff;
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break;
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case WriteMouseOutputBuff:
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DPRINTF(I8042, "Got command to write to mouse output buffer.\n");
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lastCommand = WriteMouseOutputBuff;
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break;
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case WriteToMouse:
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DPRINTF(I8042, "Expecting mouse command.\n");
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lastCommand = WriteToMouse;
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break;
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case DisableA20:
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panic("i8042 \"Disable A20\" command not implemented.\n");
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case EnableA20:
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panic("i8042 \"Enable A20\" command not implemented.\n");
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case ReadTestInputs:
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panic("i8042 \"Read test inputs\" command not implemented.\n");
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case SystemReset:
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panic("i8042 \"System reset\" command not implemented.\n");
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default:
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warn("Write to unknown i8042 "
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"(keyboard controller) command port.\n");
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}
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} else {
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panic("Write to unrecognized port %#x.\n", addr);
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}
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pkt->makeAtomicResponse();
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return latency;
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}
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void
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X86ISA::I8042::serialize(CheckpointOut &cp) const
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{
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SERIALIZE_SCALAR(dataPort);
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SERIALIZE_SCALAR(commandPort);
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SERIALIZE_SCALAR(statusReg);
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SERIALIZE_SCALAR(commandByte);
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SERIALIZE_SCALAR(dataReg);
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SERIALIZE_SCALAR(lastCommand);
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}
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void
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X86ISA::I8042::unserialize(CheckpointIn &cp)
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{
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UNSERIALIZE_SCALAR(dataPort);
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UNSERIALIZE_SCALAR(commandPort);
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UNSERIALIZE_SCALAR(statusReg);
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UNSERIALIZE_SCALAR(commandByte);
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UNSERIALIZE_SCALAR(dataReg);
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UNSERIALIZE_SCALAR(lastCommand);
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}
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X86ISA::I8042 *
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I8042Params::create()
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{
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return new X86ISA::I8042(this);
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}
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