Joel Hestness 467093ebf2 ruby: tag and data cache access support ...

Updates to Ruby to support statistics counting of cache accesses.  This feature
serves multiple purposes beyond simple stats collection.  It provides the
foundation for ruby to model the cache tag and data arrays as physical
resources, as well as provide the necessary input data for McPAT power
modeling.

2012-07-10 22:51:54 -07:00

..

cache

Port: Align port names in C++ and Python

2012-07-09 12:35:39 -04:00

config

Fixes to get prefetching working again.

2009-02-16 08:56:40 -08:00

protocol

ruby: tag and data cache access support

2012-07-10 22:51:54 -07:00

ruby

ruby: tag and data cache access support

2012-07-10 22:51:54 -07:00

slicc

ruby: tag and data cache access support

2012-07-10 22:51:54 -07:00

abstract_mem.cc

Mem: Make members relating to range and size constant

2012-07-09 12:35:44 -04:00

abstract_mem.hh

Mem: Make members relating to range and size constant

2012-07-09 12:35:44 -04:00

AbstractMemory.py

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

bridge.cc

Port: Align port names in C++ and Python

2012-07-09 12:35:39 -04:00

bridge.hh

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

Bridge.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

bus.cc

Bus: Split the bus into separate request/response layers

2012-07-09 12:35:37 -04:00

bus.hh

Bus: Split the bus into separate request/response layers

2012-07-09 12:35:37 -04:00

Bus.py

Bus: Make the default bus width 8 bytes instead of 64

2012-07-09 12:35:38 -04:00

coherent_bus.cc

Port: Align port names in C++ and Python

2012-07-09 12:35:39 -04:00

coherent_bus.hh

Bus: Split the bus into separate request/response layers

2012-07-09 12:35:37 -04:00

comm_monitor.cc

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

comm_monitor.hh

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

CommMonitor.py

MEM: Add the communication monitor

2012-05-09 04:37:45 -04:00

fs_translating_port_proxy.cc

mem: fix bug with CopyStringOut and null string termination.

2012-05-10 18:04:27 -05:00

fs_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

mem_object.cc

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

mem_object.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

MemObject.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

mport.cc

MEM: Separate snoops and normal memory requests/responses

2012-04-14 05:45:07 -04:00

mport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

noncoherent_bus.cc

Port: Align port names in C++ and Python

2012-07-09 12:35:39 -04:00

noncoherent_bus.hh

Bus: Split the bus into separate request/response layers

2012-07-09 12:35:37 -04:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet_queue.cc

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

packet_queue.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

packet.cc

Packet: Cleaning up packet command and attribute

2012-05-23 09:18:04 -04:00

packet.hh

sim: Remove FastAlloc

2012-06-05 01:23:08 -04:00

page_table.cc

Fix: Address a few benign memory leaks

2012-07-09 12:35:30 -04:00

page_table.hh

SE/FS: Get rid of includes of config/full_system.hh.

2011-11-18 02:20:22 -08:00

physical.cc

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

physical.hh

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

port_proxy.cc

MEM: Remove the Broadcast destination from the packet

2012-04-14 05:45:55 -04:00

port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

port.cc

Port: Add getAddrRanges to master port (asking slave port)

2012-07-09 12:35:33 -04:00

port.hh

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

qport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

request.hh

sim: Remove FastAlloc

2012-06-05 01:23:08 -04:00

SConscript

ruby: tag and data cache access support

2012-07-10 22:51:54 -07:00

se_translating_port_proxy.cc

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

se_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

simple_mem.cc

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

simple_mem.hh

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

SimpleMemory.py

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

tport.cc

Port: Hide the queue implementation in SimpleTimingPort

2012-07-09 12:35:42 -04:00

tport.hh

Port: Hide the queue implementation in SimpleTimingPort

2012-07-09 12:35:42 -04:00