458c98082c
This is the final step in the transformation process. We limit the use of the "managing Exception Level" for a translation in favour of the more standard "Translation Regime" This greatly simplifies our code, especially with VHE where the managing el (EL2) could handle to different translation regimes (EL and EL2&0). We can therefore remove the isHost flag wherever it got used. That case is automatically handled by the proper regime value (EL2&0) Change-Id: Iafd1d2ce4757cfa6598656759694e5e7b05267ad Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
382 lines
13 KiB
C++
382 lines
13 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013, 2016-2020, 2022-2023 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_UTILITY_HH__
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#define __ARCH_ARM_UTILITY_HH__
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#include "arch/arm/regs/cc.hh"
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#include "arch/arm/regs/int.hh"
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#include "arch/arm/regs/misc.hh"
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#include "arch/arm/types.hh"
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#include "base/logging.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "enums/ArmExtension.hh"
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namespace gem5
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{
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class ArmSystem;
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namespace ArmISA
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{
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inline bool
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testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
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{
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bool n = (nz & 0x2);
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bool z = (nz & 0x1);
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switch (code) {
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case COND_EQ: return z;
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case COND_NE: return !z;
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case COND_CS: return c;
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case COND_CC: return !c;
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case COND_MI: return n;
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case COND_PL: return !n;
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case COND_VS: return v;
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case COND_VC: return !v;
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case COND_HI: return (c && !z);
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case COND_LS: return !(c && !z);
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case COND_GE: return !(n ^ v);
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case COND_LT: return (n ^ v);
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case COND_GT: return !(n ^ v || z);
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case COND_LE: return (n ^ v || z);
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case COND_AL: return true;
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case COND_UC: return true;
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default:
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panic("Unhandled predicate condition: %d\n", code);
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}
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}
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/** Send an event (SEV) to a specific PE if there isn't
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* already a pending event */
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void sendEvent(ThreadContext *tc);
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static inline bool
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inUserMode(CPSR cpsr)
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{
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return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
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}
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static inline bool
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inPrivilegedMode(CPSR cpsr)
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{
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return !inUserMode(cpsr);
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}
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bool isSecure(ThreadContext *tc);
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bool inAArch64(ThreadContext *tc);
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/**
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* Returns the current Exception Level (EL) of the
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* provided ThreadContext
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*/
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ExceptionLevel currEL(const ThreadContext *tc);
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inline ExceptionLevel
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currEL(CPSR cpsr)
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{
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return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
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}
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/**
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* Returns true if the provided ThreadContext supports the ArmExtension
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* passed as a second argument.
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*/
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bool HaveExt(ThreadContext *tc, ArmExtension ext);
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bool IsSecureEL2Enabled(ThreadContext *tc);
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bool EL2Enabled(ThreadContext *tc);
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/**
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* This function checks whether selected EL provided as an argument
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* is using the AArch32 ISA. This information might be unavailable
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* at the current EL status: it hence returns a pair of boolean values:
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* a first boolean, true if information is available (known),
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* and a second one, true if EL is using AArch32, false for AArch64.
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*
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* @param tc The thread context.
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* @param el The target exception level.
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* @retval known is FALSE for EL0 if the current Exception level
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* is not EL0 and EL1 is using AArch64, since it cannot
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* determine the state of EL0; TRUE otherwise.
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* @retval aarch32 is TRUE if the specified Exception level is using AArch32;
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* FALSE otherwise.
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*/
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std::pair<bool, bool> ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el);
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std::pair<bool, bool> ELStateUsingAArch32K(ThreadContext *tc,
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ExceptionLevel el, bool secure);
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bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure);
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bool ELIs32(ThreadContext *tc, ExceptionLevel el);
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bool ELIs64(ThreadContext *tc, ExceptionLevel el);
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/**
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* Returns true if the current exception level `el` is executing a Host OS or
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* an application of a Host OS (Armv8.1 Virtualization Host Extensions).
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*/
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bool ELIsInHost(ThreadContext *tc, ExceptionLevel el);
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ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure);
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bool isBigEndian64(const ThreadContext *tc);
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/**
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* badMode is checking if the execution mode provided as an argument is
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* valid and implemented for AArch32
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*
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* @param tc ThreadContext
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* @param mode OperatingMode to check
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* @return false if mode is valid and implemented, true otherwise
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*/
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bool badMode32(ThreadContext *tc, OperatingMode mode);
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/**
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* badMode is checking if the execution mode provided as an argument is
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* valid and implemented.
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*
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* @param tc ThreadContext
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* @param mode OperatingMode to check
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* @return false if mode is valid and implemented, true otherwise
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*/
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bool badMode(ThreadContext *tc, OperatingMode mode);
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static inline uint8_t
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itState(CPSR psr)
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{
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ITSTATE it = 0;
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it.top6 = psr.it2;
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it.bottom2 = psr.it1;
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return (uint8_t)it;
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}
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ExceptionLevel s1TranslationRegime(ThreadContext *tc, ExceptionLevel el);
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/**
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* Removes the tag from tagged addresses if that mode is enabled.
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* @param addr The address to be purified.
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* @param tc The thread context.
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* @param el The controlled exception level.
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* @return The purified address.
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*/
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Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
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TCR tcr, bool isInstr);
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Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
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bool isInstr);
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Addr maskTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
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int topbit);
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int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
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TCR tcr, ExceptionLevel el);
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bool isSecureBelowEL3(ThreadContext *tc);
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bool longDescFormatInUse(ThreadContext *tc);
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/** This helper function is either returing the value of
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* MPIDR_EL1 (by calling getMPIDR), or it is issuing a read
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* to VMPIDR_EL2 (as it happens in virtualized systems) */
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RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
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/** This helper function is returning the value of MPIDR_EL1 */
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RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
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/** Retrieves MPIDR_EL1.{Aff2,Aff1,Aff0} affinity numbers */
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Affinity getAffinity(ArmSystem *arm_sys, ThreadContext *tc);
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static inline uint32_t
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mcrMrcIssBuild(bool isRead, uint32_t crm, RegIndex rt, uint32_t crn,
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uint32_t opc1, uint32_t opc2)
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{
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return (isRead << 0) |
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(crm << 1) |
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(rt << 5) |
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(crn << 10) |
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(opc1 << 14) |
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(opc2 << 17);
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}
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static inline void
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mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, RegIndex &rt,
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uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
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{
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isRead = (iss >> 0) & 0x1;
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crm = (iss >> 1) & 0xF;
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rt = (RegIndex)((iss >> 5) & 0xF);
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crn = (iss >> 10) & 0xF;
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opc1 = (iss >> 14) & 0x7;
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opc2 = (iss >> 17) & 0x7;
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}
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static inline uint32_t
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mcrrMrrcIssBuild(bool isRead, uint32_t crm, RegIndex rt, RegIndex rt2,
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uint32_t opc1)
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{
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return (isRead << 0) |
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(crm << 1) |
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(rt << 5) |
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(rt2 << 10) |
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(opc1 << 16);
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}
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Fault mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
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ThreadContext *tc, uint32_t imm);
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bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
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uint32_t iss, ExceptionClass *ec=nullptr);
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bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
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uint32_t iss);
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Fault mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
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ThreadContext *tc, uint32_t imm);
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bool mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
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uint32_t iss, ExceptionClass *ec=nullptr);
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Fault AArch64AArch32SystemAccessTrap(const MiscRegIndex miscReg,
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ExtMachInst machInst, ThreadContext *tc,
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uint32_t imm, ExceptionClass ec);
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bool isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isGenericTimerHypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
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ExceptionClass *ec);
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bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isGenericTimerCommonEL0HypTrap(const MiscRegIndex miscReg,
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ThreadContext *tc, ExceptionClass *ec);
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bool isGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
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ExceptionClass *ec);
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bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg,
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ThreadContext *tc);
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bool SPAlignmentCheckEnabled(ThreadContext *tc);
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Addr truncPage(Addr addr);
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Addr roundPage(Addr addr);
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// Decodes the register index to access based on the fields used in a MSR
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// or MRS instruction
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bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
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CPSR cpsr, SCR scr, NSACR nsacr,
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bool checkSecurity=true);
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// This wrapper function is used to turn the register index into a source
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// parameter for the instruction. See Operands.isa
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static inline int
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decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
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{
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int regIdx;
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bool isIntReg;
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bool validReg;
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validReg = decodeMrsMsrBankedReg(
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sysM, r, isIntReg, regIdx, 0, 0, 0, false);
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return (validReg && isIntReg) ? regIdx : int_reg::Zero;
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}
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/**
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* Returns the n. of PA bits corresponding to the specified encoding.
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*/
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int decodePhysAddrRange64(uint8_t pa_enc);
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/**
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* Returns the encoding corresponding to the specified n. of PA bits.
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*/
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uint8_t encodePhysAddrRange64(int pa_size);
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inline ByteOrder
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byteOrder(const ThreadContext *tc)
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{
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return isBigEndian64(tc) ? ByteOrder::big : ByteOrder::little;
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};
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bool isUnpriviledgeAccess(ThreadContext *tc);
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void syncVecRegsToElems(ThreadContext *tc);
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void syncVecElemsToRegs(ThreadContext *tc);
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bool fgtEnabled(ThreadContext *tc);
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bool isHcrxEL2Enabled(ThreadContext *tc);
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TranslationRegime translationRegime(ThreadContext *tc, ExceptionLevel el);
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static inline bool
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useVMID(TranslationRegime regime)
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{
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return regime == TranslationRegime::EL10;
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}
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} // namespace ArmISA
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} // namespace gem5
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#endif
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