452217817f
This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
145 lines
3.8 KiB
C++
145 lines
3.8 KiB
C++
/*
|
|
* Copyright (c) 2009 Advanced Micro Devices, Inc.
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
* Authors: Tushar Krishna
|
|
*/
|
|
|
|
#ifndef __CPU_NETWORKTEST_NETWORKTEST_HH__
|
|
#define __CPU_NETWORKTEST_NETWORKTEST_HH__
|
|
|
|
#include <set>
|
|
|
|
#include "base/statistics.hh"
|
|
#include "mem/mem_object.hh"
|
|
#include "mem/port.hh"
|
|
#include "params/NetworkTest.hh"
|
|
#include "sim/eventq.hh"
|
|
#include "sim/sim_exit.hh"
|
|
#include "sim/sim_object.hh"
|
|
#include "sim/stats.hh"
|
|
|
|
class Packet;
|
|
class NetworkTest : public MemObject
|
|
{
|
|
public:
|
|
typedef NetworkTestParams Params;
|
|
NetworkTest(const Params *p);
|
|
|
|
virtual void init();
|
|
|
|
// main simulation loop (one cycle)
|
|
void tick();
|
|
|
|
virtual MasterPort &getMasterPort(const std::string &if_name,
|
|
int idx = -1);
|
|
|
|
/**
|
|
* Print state of address in memory system via PrintReq (for
|
|
* debugging).
|
|
*/
|
|
void printAddr(Addr a);
|
|
|
|
protected:
|
|
class TickEvent : public Event
|
|
{
|
|
private:
|
|
NetworkTest *cpu;
|
|
|
|
public:
|
|
TickEvent(NetworkTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
|
|
void process() { cpu->tick(); }
|
|
virtual const char *description() const { return "NetworkTest tick"; }
|
|
};
|
|
|
|
TickEvent tickEvent;
|
|
|
|
class CpuPort : public MasterPort
|
|
{
|
|
NetworkTest *networktest;
|
|
|
|
public:
|
|
|
|
CpuPort(const std::string &_name, NetworkTest *_networktest)
|
|
: MasterPort(_name, _networktest), networktest(_networktest)
|
|
{ }
|
|
|
|
protected:
|
|
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
|
|
|
virtual void recvRetry();
|
|
};
|
|
|
|
CpuPort cachePort;
|
|
|
|
class NetworkTestSenderState : public Packet::SenderState
|
|
{
|
|
public:
|
|
/** Constructor. */
|
|
NetworkTestSenderState(uint8_t *_data)
|
|
: data(_data)
|
|
{ }
|
|
|
|
// Hold onto data pointer
|
|
uint8_t *data;
|
|
};
|
|
|
|
PacketPtr retryPkt;
|
|
unsigned size;
|
|
int id;
|
|
|
|
unsigned blockSizeBits;
|
|
|
|
Tick noResponseCycles;
|
|
|
|
int numMemories;
|
|
Tick simCycles;
|
|
bool fixedPkts;
|
|
int maxPackets;
|
|
int numPacketsSent;
|
|
|
|
int trafficType;
|
|
double injRate;
|
|
int precision;
|
|
|
|
MasterID masterId;
|
|
|
|
void completeRequest(PacketPtr pkt);
|
|
|
|
void generatePkt();
|
|
void sendPkt(PacketPtr pkt);
|
|
|
|
void doRetry();
|
|
|
|
friend class MemCompleteEvent;
|
|
};
|
|
|
|
#endif // __CPU_NETWORKTEST_NETWORKTEST_HH__
|
|
|
|
|
|
|