Jason Power 44b4c96253 Ruby: Add RubySystem parameter to MemoryControl ...

This guarantees that RubySystem object is created before the MemoryController
object is created.

2012-08-16 23:39:36 -05:00

..

cache

O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs

2012-08-15 10:38:08 -04:00

config

Fixes to get prefetching working again.

2009-02-16 08:56:40 -08:00

protocol

Ruby: remove some unused stuff from SLICC files

2012-07-12 08:39:18 -05:00

ruby

Ruby: Add RubySystem parameter to MemoryControl

2012-08-16 23:39:36 -05:00

slicc

imported patch jason/slicc-external-structure-fix

2012-07-10 22:51:54 -07:00

abstract_mem.cc

Mem: Make members relating to range and size constant

2012-07-09 12:35:44 -04:00

abstract_mem.hh

Mem: Make members relating to range and size constant

2012-07-09 12:35:44 -04:00

AbstractMemory.py

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

bridge.cc

Port: Align port names in C++ and Python

2012-07-09 12:35:39 -04:00

bridge.hh

Bridge: Use EventWrapper instead of Event subclass for sendEvent

2012-07-23 09:32:19 -04:00

Bridge.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

bus.cc

O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs

2012-08-15 10:38:08 -04:00

bus.hh

Bus: Split the bus into separate request/response layers

2012-07-09 12:35:37 -04:00

Bus.py

Bus: Make the default bus width 8 bytes instead of 64

2012-07-09 12:35:38 -04:00

coherent_bus.cc

Port: Align port names in C++ and Python

2012-07-09 12:35:39 -04:00

coherent_bus.hh

Bus: Split the bus into separate request/response layers

2012-07-09 12:35:37 -04:00

comm_monitor.cc

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

comm_monitor.hh

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

CommMonitor.py

MEM: Add the communication monitor

2012-05-09 04:37:45 -04:00

fs_translating_port_proxy.cc

mem: fix bug with CopyStringOut and null string termination.

2012-05-10 18:04:27 -05:00

fs_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

mem_object.cc

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

mem_object.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

MemObject.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

mport.cc

MEM: Separate snoops and normal memory requests/responses

2012-04-14 05:45:07 -04:00

mport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

noncoherent_bus.cc

Port: Align port names in C++ and Python

2012-07-09 12:35:39 -04:00

noncoherent_bus.hh

Bus: Split the bus into separate request/response layers

2012-07-09 12:35:37 -04:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet_queue.cc

O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs

2012-08-15 10:38:08 -04:00

packet_queue.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

packet.cc

Packet: Cleaning up packet command and attribute

2012-05-23 09:18:04 -04:00

packet.hh

sim: Remove FastAlloc

2012-06-05 01:23:08 -04:00

page_table.cc

Fix: Address a few benign memory leaks

2012-07-09 12:35:30 -04:00

page_table.hh

SE/FS: Get rid of includes of config/full_system.hh.

2011-11-18 02:20:22 -08:00

physical.cc

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

physical.hh

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

port_proxy.cc

MEM: Remove the Broadcast destination from the packet

2012-04-14 05:45:55 -04:00

port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

port.cc

O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs

2012-08-15 10:38:08 -04:00

port.hh

O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs

2012-08-15 10:38:08 -04:00

qport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

request.hh

sim: Remove FastAlloc

2012-06-05 01:23:08 -04:00

SConscript

ruby: banked cache array resource model

2012-07-10 22:51:54 -07:00

se_translating_port_proxy.cc

SETranslatingPortProxy: fix bug in tryReadString()

2012-08-06 16:57:11 -07:00

se_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

simple_mem.cc

Mem: Make SimpleMemory single ported

2012-07-12 12:56:13 -04:00

simple_mem.hh

Mem: Make SimpleMemory single ported

2012-07-12 12:56:13 -04:00

SimpleMemory.py

Mem: Make SimpleMemory single ported

2012-07-12 12:56:13 -04:00

tport.cc

Port: Hide the queue implementation in SimpleTimingPort

2012-07-09 12:35:42 -04:00

tport.hh

Port: Hide the queue implementation in SimpleTimingPort

2012-07-09 12:35:42 -04:00