bdb2820218
Change-Id: I0907a6f1ada3038305c2d83a350a8d435ac657ba Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25403 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
149 lines
3.9 KiB
C++
149 lines
3.9 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Emulation of the Malta CChip CSRs
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*/
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#include "dev/mips/malta_cchip.hh"
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/intr_control.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Malta.hh"
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#include "dev/mips/malta.hh"
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#include "dev/mips/maltareg.h"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "mem/port.hh"
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#include "params/MaltaCChip.hh"
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#include "sim/system.hh"
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using namespace std;
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MaltaCChip::MaltaCChip(Params *p)
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: BasicPioDevice(p, 0xfffffff), malta(p->malta)
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{
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warn("MaltaCCHIP::MaltaCChip() not implemented.");
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//Put back pointer in malta
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malta->cchip = this;
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}
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Tick
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MaltaCChip::read(PacketPtr pkt)
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{
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panic("MaltaCCHIP::read() not implemented.");
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return pioDelay;
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}
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Tick
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MaltaCChip::write(PacketPtr pkt)
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{
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panic("MaltaCCHIP::write() not implemented.");
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return pioDelay;
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}
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void
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MaltaCChip::clearIPI(uint64_t ipintr)
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{
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panic("MaltaCCHIP::clear() not implemented.");
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}
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void
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MaltaCChip::clearITI(uint64_t itintr)
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{
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panic("MaltaCCHIP::clearITI() not implemented.");
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}
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void
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MaltaCChip::reqIPI(uint64_t ipreq)
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{
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panic("MaltaCCHIP::reqIPI() not implemented.");
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}
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void
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MaltaCChip::postRTC()
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{
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panic("MaltaCCHIP::postRTC() not implemented.");
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}
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void
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MaltaCChip::postIntr(uint32_t interrupt)
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{
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uint64_t size = sys->threadContexts.size();
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assert(size <= Malta::Max_CPUs);
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for (int i=0; i < size; i++) {
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//Note: Malta does not use index, but this was added to use the
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//pre-existing implementation
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malta->intrctrl->post(i, interrupt, 0);
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DPRINTF(Malta, "posting interrupt to cpu %d, interrupt %d\n",
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i, interrupt);
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}
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}
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void
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MaltaCChip::clearIntr(uint32_t interrupt)
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{
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uint64_t size = sys->threadContexts.size();
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assert(size <= Malta::Max_CPUs);
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for (int i=0; i < size; i++) {
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//Note: Malta does not use index, but this was added to use the
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//pre-existing implementation
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malta->intrctrl->clear(i, interrupt, 0);
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DPRINTF(Malta, "clearing interrupt to cpu %d, interrupt %d\n",
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i, interrupt);
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}
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}
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void
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MaltaCChip::serialize(CheckpointOut &cp) const
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{
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}
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void
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MaltaCChip::unserialize(CheckpointIn &cp)
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{
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}
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MaltaCChip *
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MaltaCChipParams::create()
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{
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return new MaltaCChip(this);
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}
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