43a1ea88b8
This is the rest of the code for part 2. See http://learning.gem5.org/book/part2/simplecache.html Change-Id: I5db099266a1196914656be3858fdd5fb4f8eab48 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5023 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
48 lines
2.2 KiB
Python
48 lines
2.2 KiB
Python
# -*- coding: utf-8 -*-
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# Copyright (c) 2017 Jason Lowe-Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Jason Lowe-Power
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from m5.params import *
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from m5.proxy import *
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from MemObject import MemObject
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class SimpleCache(MemObject):
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type = 'SimpleCache'
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cxx_header = "learning_gem5/part2/simple_cache.hh"
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# Vector port example. Both the instruction and data ports connect to this
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# port which is automatically split out into two ports.
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cpu_side = VectorSlavePort("CPU side port, receives requests")
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mem_side = MasterPort("Memory side port, sends requests")
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latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")
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size = Param.MemorySize('16kB', "The size of the cache")
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system = Param.System(Parent.any, "The system this cache is part of")
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