61d95de4c8
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
Remove OOO CPU stuff.
arch/alpha/faults.hh:
Add fake memory fault. This will be removed eventually.
arch/alpha/isa_desc:
Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
Remove asid.
cpu/beta_cpu/comm.hh:
Remove global history field.
cpu/beta_cpu/commit.hh:
Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
Add debug function.
cpu/beta_cpu/decode_impl.hh:
Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
Extra forward declares added due to compile error.
--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
136 lines
2.6 KiB
C++
136 lines
2.6 KiB
C++
#ifndef __ALPHA_SIMPLE_PARAMS_HH__
|
|
#define __ALPHA_SIMPLE_PARAMS_HH__
|
|
|
|
#include "cpu/beta_cpu/full_cpu.hh"
|
|
|
|
//Forward declarations
|
|
class System;
|
|
class AlphaITB;
|
|
class AlphaDTB;
|
|
class FunctionalMemory;
|
|
class Process;
|
|
class MemInterface;
|
|
|
|
/**
|
|
* This file defines the parameters that will be used for the AlphaFullCPU.
|
|
* This must be defined externally so that the Impl can have a params class
|
|
* defined that it can pass to all of the individual stages.
|
|
*/
|
|
|
|
class AlphaSimpleParams : public BaseFullCPU::Params
|
|
{
|
|
public:
|
|
|
|
#ifdef FULL_SYSTEM
|
|
AlphaITB *itb; AlphaDTB *dtb;
|
|
#else
|
|
std::vector<Process *> workload;
|
|
Process *process;
|
|
#endif // FULL_SYSTEM
|
|
|
|
FunctionalMemory *mem;
|
|
|
|
//
|
|
// Caches
|
|
//
|
|
MemInterface *icacheInterface;
|
|
MemInterface *dcacheInterface;
|
|
|
|
//
|
|
// Fetch
|
|
//
|
|
unsigned decodeToFetchDelay;
|
|
unsigned renameToFetchDelay;
|
|
unsigned iewToFetchDelay;
|
|
unsigned commitToFetchDelay;
|
|
unsigned fetchWidth;
|
|
|
|
//
|
|
// Decode
|
|
//
|
|
unsigned renameToDecodeDelay;
|
|
unsigned iewToDecodeDelay;
|
|
unsigned commitToDecodeDelay;
|
|
unsigned fetchToDecodeDelay;
|
|
unsigned decodeWidth;
|
|
|
|
//
|
|
// Rename
|
|
//
|
|
unsigned iewToRenameDelay;
|
|
unsigned commitToRenameDelay;
|
|
unsigned decodeToRenameDelay;
|
|
unsigned renameWidth;
|
|
|
|
//
|
|
// IEW
|
|
//
|
|
unsigned commitToIEWDelay;
|
|
unsigned renameToIEWDelay;
|
|
unsigned issueToExecuteDelay;
|
|
unsigned issueWidth;
|
|
unsigned executeWidth;
|
|
unsigned executeIntWidth;
|
|
unsigned executeFloatWidth;
|
|
unsigned executeBranchWidth;
|
|
unsigned executeMemoryWidth;
|
|
|
|
//
|
|
// Commit
|
|
//
|
|
unsigned iewToCommitDelay;
|
|
unsigned renameToROBDelay;
|
|
unsigned commitWidth;
|
|
unsigned squashWidth;
|
|
|
|
//
|
|
// Branch predictor (BP & BTB)
|
|
//
|
|
/*
|
|
unsigned localPredictorSize;
|
|
unsigned localPredictorCtrBits;
|
|
*/
|
|
|
|
unsigned local_predictor_size;
|
|
unsigned local_ctr_bits;
|
|
unsigned local_history_table_size;
|
|
unsigned local_history_bits;
|
|
unsigned global_predictor_size;
|
|
unsigned global_ctr_bits;
|
|
unsigned global_history_bits;
|
|
unsigned choice_predictor_size;
|
|
unsigned choice_ctr_bits;
|
|
|
|
unsigned BTBEntries;
|
|
unsigned BTBTagSize;
|
|
|
|
unsigned RASSize;
|
|
|
|
//
|
|
// Load store queue
|
|
//
|
|
unsigned LQEntries;
|
|
unsigned SQEntries;
|
|
|
|
//
|
|
// Memory dependence
|
|
//
|
|
unsigned SSITSize;
|
|
unsigned LFSTSize;
|
|
|
|
//
|
|
// Miscellaneous
|
|
//
|
|
unsigned numPhysIntRegs;
|
|
unsigned numPhysFloatRegs;
|
|
unsigned numIQEntries;
|
|
unsigned numROBEntries;
|
|
|
|
// Probably can get this from somewhere.
|
|
unsigned instShiftAmt;
|
|
|
|
bool defReg;
|
|
};
|
|
|
|
#endif
|