Giacomo Travaglini 42fb1d657c stdlib: Add DTB generation capabilites to AbstractCacheHierarchy ...

Now that we are able to provide a view of the cache hierarchy from
the python world, we can start generating DTB entries for caches
and more specifically to properly fill the next-level-cache and
cache-level properties

Change-Id: Iba9ea08fe605f77a353c9e64d62b04b80478b4e2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2024-03-26 13:14:35 +00:00

..

arch

arch-riscv: adding vector unit-stride segment stores to RISC-V (#913)

2024-03-22 15:45:58 -07:00

base

base: Add a check for edge case

2024-01-23 11:35:54 -08:00

cpu

arch-riscv: adding vector unit-stride segment stores to RISC-V (#913)

2024-03-22 15:45:58 -07:00

dev

dev-amdgpu: Support multiple CPs and MMIO AddrRanges

2024-03-21 10:13:55 -05:00

doc

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doxygen

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gpu-compute

gpu-compute: Add support for skipping GPU kernels (#940)

2024-03-21 07:46:27 -07:00

kern

misc: Fix 'maybe-uninitialized' warn turn off (#706)

2023-12-21 18:45:56 -08:00

learning_gem5

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

mem

mem: Fix callback of functional access in port wrapper (#938)

2024-03-18 08:21:43 -07:00

proto

scons: Use Kconfig to configure gem5.

2023-11-23 08:26:10 +08:00

python

stdlib: Add DTB generation capabilites to AbstractCacheHierarchy

2024-03-26 13:14:35 +00:00

sim

sim-se: Catch None value if binary is not compatible with gem5 (#903)

2024-03-01 16:41:18 -08:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

systemc: Reduce unnecessary backdoor request in atomic transaction (#795)

2024-02-05 11:08:20 -08:00

Doxyfile

misc: Change version information to develop for v24.0

2023-12-27 12:29:52 -08:00

Kconfig

scons: Add new config option HAVE_CAPSTONE to Kconfig

2023-11-23 08:26:11 +08:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00