42b56ceb7b
The memory manager is responsible for reading and writes to VRAM memory for direct requests that bypass GPU caches. Change-Id: I4aa1e77737ce52f2f2c01929b58984126bdcb925 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51850 Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
114 lines
3.7 KiB
C++
114 lines
3.7 KiB
C++
/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_AMDGPU_MEMORY_MANAGER_HH__
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#define __DEV_AMDGPU_MEMORY_MANAGER_HH__
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#include <deque>
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#include "base/callback.hh"
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#include "mem/port.hh"
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#include "params/AMDGPUMemoryManager.hh"
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#include "sim/clocked_object.hh"
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namespace gem5
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{
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class AMDGPUMemoryManager : public ClockedObject
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{
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class GPUMemPort : public MasterPort
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{
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public:
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GPUMemPort(const std::string &_name, AMDGPUMemoryManager *_gpuMemMgr)
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: MasterPort(_name, _gpuMemMgr)
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{
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}
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bool recvTimingResp(PacketPtr pkt) override;
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void recvReqRetry() override;
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struct SenderState : public Packet::SenderState
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{
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SenderState(Event *callback, Addr addr)
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: _callback(callback), _addr(addr)
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{}
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Event *_callback;
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Addr _addr;
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};
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std::deque<PacketPtr> retries;
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};
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GPUMemPort _gpuMemPort;
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const int cacheLineSize;
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const RequestorID _requestorId;
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public:
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AMDGPUMemoryManager(const AMDGPUMemoryManagerParams &p);
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~AMDGPUMemoryManager() {};
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/**
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* Write size amount of data to device memory at addr using flags and
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* callback.
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*
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* @param addr Device address to write.
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* @param data Pointer to data to write.
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* @param size Number of bytes to write.
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* @param flag Additional request flags for write packets.
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* @param callback Event callback to call after all bytes are written.
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*/
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void writeRequest(Addr addr, uint8_t *data, int size,
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Request::Flags flag = 0, Event *callback = nullptr);
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/**
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* Get the requestorID for the memory manager. This ID is used for all
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* packets which should be routed through the device network.
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*
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* @return requestorID of this object.
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*/
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RequestorID getRequestorID() const { return _requestorId; }
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Port &
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getPort(const std::string &if_name, PortID idx) override
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{
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if (if_name == "port") {
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return _gpuMemPort;
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} else {
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return ClockedObject::getPort(if_name, idx);
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}
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}
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};
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} // namespace gem5
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#endif // __DEV_AMDGPU_MEMORY_MANAGER_HH__
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