413ba1fdaf
Track the point in the initialization where statistics have been registered. After this point registering new masterIds can no longer work as some SimObjects may have sized stats vectors based on the previous value. If someone tries to register a masterId after this point the simulator executes fatal().
443 lines
12 KiB
C++
443 lines
12 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* Copyright (c) 2011 Regents of the University of California
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Lisa Hsu
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* Nathan Binkert
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* Ali Saidi
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* Rick Strong
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*/
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#include "arch/isa_traits.hh"
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#include "arch/remote_gdb.hh"
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#include "arch/utility.hh"
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#include "arch/vtophys.hh"
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#include "base/loader/object_file.hh"
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#include "base/loader/symtab.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Loader.hh"
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#include "debug/WorkItems.hh"
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#include "kern/kernel_stats.hh"
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#include "mem/physical.hh"
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#include "params/System.hh"
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#include "sim/byteswap.hh"
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#include "sim/debug.hh"
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#include "sim/full_system.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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vector<System *> System::systemList;
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int System::numSystemsRunning = 0;
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System::System(Params *p)
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: MemObject(p), _systemPort("system_port", this),
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_numContexts(0),
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pagePtr(0),
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init_param(p->init_param),
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physProxy(_systemPort),
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virtProxy(_systemPort),
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loadAddrMask(p->load_addr_mask),
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nextPID(0),
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physmem(p->memories),
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memoryMode(p->mem_mode),
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workItemsBegin(0),
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workItemsEnd(0),
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numWorkIds(p->num_work_ids),
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_params(p),
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totalNumInsts(0),
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instEventQueue("system instruction-based event queue")
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{
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// add self to global system list
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systemList.push_back(this);
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if (FullSystem) {
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kernelSymtab = new SymbolTable;
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if (!debugSymbolTable)
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debugSymbolTable = new SymbolTable;
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}
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// Get the generic system master IDs
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MasterID tmp_id M5_VAR_USED;
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tmp_id = getMasterId("writebacks");
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assert(tmp_id == Request::wbMasterId);
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tmp_id = getMasterId("functional");
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assert(tmp_id == Request::funcMasterId);
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tmp_id = getMasterId("interrupt");
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assert(tmp_id == Request::intMasterId);
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if (FullSystem) {
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if (params()->kernel == "") {
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inform("No kernel set for full system simulation. "
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"Assuming you know what you're doing if not SPARC ISA\n");
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} else {
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// Get the kernel code
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kernel = createObjectFile(params()->kernel);
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inform("kernel located at: %s", params()->kernel);
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if (kernel == NULL)
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fatal("Could not load kernel file %s", params()->kernel);
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// setup entry points
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kernelStart = kernel->textBase();
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kernelEnd = kernel->bssBase() + kernel->bssSize();
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kernelEntry = kernel->entryPoint();
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// load symbols
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if (!kernel->loadGlobalSymbols(kernelSymtab))
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fatal("could not load kernel symbols\n");
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if (!kernel->loadLocalSymbols(kernelSymtab))
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fatal("could not load kernel local symbols\n");
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if (!kernel->loadGlobalSymbols(debugSymbolTable))
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fatal("could not load kernel symbols\n");
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if (!kernel->loadLocalSymbols(debugSymbolTable))
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fatal("could not load kernel local symbols\n");
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// Loading only needs to happen once and after memory system is
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// connected so it will happen in initState()
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}
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}
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// increment the number of running systms
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numSystemsRunning++;
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}
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System::~System()
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{
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delete kernelSymtab;
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delete kernel;
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for (uint32_t j = 0; j < numWorkIds; j++)
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delete workItemStats[j];
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}
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void
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System::init()
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{
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// check that the system port is connected
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if (!_systemPort.isConnected())
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panic("System port on %s is not connected.\n", name());
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}
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MasterPort&
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System::getMasterPort(const std::string &if_name, int idx)
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{
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// no need to distinguish at the moment (besides checking)
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return _systemPort;
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}
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void
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System::setMemoryMode(Enums::MemoryMode mode)
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{
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assert(getState() == Drained);
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memoryMode = mode;
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}
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bool System::breakpoint()
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{
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if (remoteGDB.size())
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return remoteGDB[0]->breakpoint();
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return false;
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}
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/**
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* Setting rgdb_wait to a positive integer waits for a remote debugger to
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* connect to that context ID before continuing. This should really
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be a parameter on the CPU object or something...
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*/
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int rgdb_wait = -1;
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int
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System::registerThreadContext(ThreadContext *tc, int assigned)
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{
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int id;
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if (assigned == -1) {
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for (id = 0; id < threadContexts.size(); id++) {
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if (!threadContexts[id])
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break;
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}
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if (threadContexts.size() <= id)
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threadContexts.resize(id + 1);
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} else {
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if (threadContexts.size() <= assigned)
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threadContexts.resize(assigned + 1);
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id = assigned;
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}
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if (threadContexts[id])
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fatal("Cannot have two CPUs with the same id (%d)\n", id);
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threadContexts[id] = tc;
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_numContexts++;
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int port = getRemoteGDBPort();
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if (port) {
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RemoteGDB *rgdb = new RemoteGDB(this, tc);
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GDBListener *gdbl = new GDBListener(rgdb, port + id);
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gdbl->listen();
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if (rgdb_wait != -1 && rgdb_wait == id)
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gdbl->accept();
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if (remoteGDB.size() <= id) {
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remoteGDB.resize(id + 1);
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}
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remoteGDB[id] = rgdb;
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}
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activeCpus.push_back(false);
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return id;
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}
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int
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System::numRunningContexts()
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{
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int running = 0;
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for (int i = 0; i < _numContexts; ++i) {
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if (threadContexts[i]->status() != ThreadContext::Halted)
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++running;
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}
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return running;
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}
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void
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System::initState()
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{
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int i;
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if (FullSystem) {
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for (i = 0; i < threadContexts.size(); i++)
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TheISA::startupCPU(threadContexts[i], i);
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// Moved from the constructor to here since it relies on the
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// address map being resolved in the interconnect
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/**
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* Load the kernel code into memory
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*/
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if (params()->kernel != "") {
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// Load program sections into memory
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kernel->loadSections(physProxy, loadAddrMask);
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DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
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DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd);
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DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
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DPRINTF(Loader, "Kernel loaded...\n");
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}
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}
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activeCpus.clear();
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if (!FullSystem)
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return;
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for (i = 0; i < threadContexts.size(); i++)
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TheISA::startupCPU(threadContexts[i], i);
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}
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void
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System::replaceThreadContext(ThreadContext *tc, int context_id)
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{
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if (context_id >= threadContexts.size()) {
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panic("replaceThreadContext: bad id, %d >= %d\n",
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context_id, threadContexts.size());
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}
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threadContexts[context_id] = tc;
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if (context_id < remoteGDB.size())
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remoteGDB[context_id]->replaceThreadContext(tc);
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}
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Addr
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System::allocPhysPages(int npages)
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{
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Addr return_addr = pagePtr << LogVMPageSize;
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pagePtr += npages;
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if (pagePtr > physmem.totalSize())
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fatal("Out of memory, please increase size of physical memory.");
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return return_addr;
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}
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Addr
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System::memSize() const
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{
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return physmem.totalSize();
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}
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Addr
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System::freeMemSize() const
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{
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return physmem.totalSize() - (pagePtr << LogVMPageSize);
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}
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bool
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System::isMemAddr(Addr addr) const
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{
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return physmem.isMemAddr(addr);
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}
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void
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System::resume()
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{
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SimObject::resume();
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totalNumInsts = 0;
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}
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void
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System::serialize(ostream &os)
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{
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if (FullSystem)
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kernelSymtab->serialize("kernel_symtab", os);
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SERIALIZE_SCALAR(pagePtr);
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SERIALIZE_SCALAR(nextPID);
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}
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void
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System::unserialize(Checkpoint *cp, const string §ion)
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{
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if (FullSystem)
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kernelSymtab->unserialize("kernel_symtab", cp, section);
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UNSERIALIZE_SCALAR(pagePtr);
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UNSERIALIZE_SCALAR(nextPID);
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}
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void
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System::regStats()
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{
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for (uint32_t j = 0; j < numWorkIds ; j++) {
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workItemStats[j] = new Stats::Histogram();
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stringstream namestr;
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ccprintf(namestr, "work_item_type%d", j);
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workItemStats[j]->init(20)
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.name(name() + "." + namestr.str())
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.desc("Run time stat for" + namestr.str())
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.prereq(*workItemStats[j]);
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}
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}
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void
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System::workItemEnd(uint32_t tid, uint32_t workid)
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{
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std::pair<uint32_t,uint32_t> p(tid, workid);
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if (!lastWorkItemStarted.count(p))
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return;
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Tick samp = curTick() - lastWorkItemStarted[p];
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DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp);
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if (workid >= numWorkIds)
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fatal("Got workid greater than specified in system configuration\n");
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workItemStats[workid]->sample(samp);
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lastWorkItemStarted.erase(p);
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}
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void
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System::printSystems()
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{
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vector<System *>::iterator i = systemList.begin();
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vector<System *>::iterator end = systemList.end();
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for (; i != end; ++i) {
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System *sys = *i;
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cerr << "System " << sys->name() << ": " << hex << sys << endl;
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}
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}
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void
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printSystems()
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{
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System::printSystems();
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}
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MasterID
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System::getMasterId(std::string master_name)
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{
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// strip off system name if the string starts with it
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if (master_name.size() > name().size() &&
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master_name.compare(0, name().size(), name()) == 0)
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master_name = master_name.erase(0, name().size() + 1);
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// CPUs in switch_cpus ask for ids again after switching
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for (int i = 0; i < masterIds.size(); i++) {
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if (masterIds[i] == master_name) {
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return i;
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}
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}
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// Verify that the statistics haven't been enabled yet
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// Otherwise objects will have sized their stat buckets and
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// they will be too small
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if (Stats::enabled())
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fatal("Can't request a masterId after regStats(). \
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You must do so in init().\n");
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masterIds.push_back(master_name);
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return masterIds.size() - 1;
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}
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std::string
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System::getMasterName(MasterID master_id)
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{
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if (master_id >= masterIds.size())
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fatal("Invalid master_id passed to getMasterName()\n");
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return masterIds[master_id];
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}
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const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
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"timing"};
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System *
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SystemParams::create()
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{
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return new System(this);
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}
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