Giacomo Travaglini 4fbe6cf419 arch-arm: Use isSecure variable for Stage2Lookup ...

TLB entries are tagged with the security state of the cpu instead
of the security attribute of the physical address

Change-Id: I728ba1c841de1ec6c1ee03aee012b185c968d078
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32639
Tested-by: kokoro <noreply+kokoro@google.com>

2020-08-14 13:07:41 +00:00

..

arch

arch-arm: Use isSecure variable for Stage2Lookup

2020-08-14 13:07:41 +00:00

base

base,scons: -wno-deprecated-copy added for hdf5.cc with GCC

2020-07-29 00:35:00 +00:00

cpu

cpu-simple: Fix BaseSimpleCPU to reset group stats

2020-08-12 02:17:58 +00:00

dev

gpu-compute: Fixing HSA's barrier bit implementation

2020-08-13 02:08:27 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

misc,sim: Tagged API methods in sim/simobject.hh

2020-05-19 21:58:24 +00:00

gpu-compute

arch-gcn3,gpu-compute: Fix GCN3 related compiler errors

2020-07-20 14:53:13 +00:00

kern

arch,cpu,sim: Eliminate the now empty kernel statistics classes.

2020-06-17 19:54:41 +00:00

learning_gem5

misc: Make many includes explicit.

2020-06-03 19:42:46 +00:00

mem

mem-ruby: Fix debug prints for regular Stores

2020-08-13 19:48:30 +00:00

proto

misc: Use the protobuf version to choose between ByteSize(Long).

2020-04-29 21:46:11 +00:00

python

util,scons: improve compareVersions function

2020-07-31 18:40:30 +00:00

sim

sim-se: don't wake up SE futex syscalls on ARM events

2020-08-10 08:52:03 +00:00

systemc

systemc: Adjust some type names in a couple tests.

2020-08-05 23:53:45 +00:00

unittest

arch,base,cpu,kerm,sim: Build a symbol table for object files.

2020-06-09 23:37:29 +00:00

Doxyfile

misc: Reverting version numbers

2020-07-03 20:59:44 -07:00

SConscript

scons: Remove the plumbing for running regression tests from scons.

2020-08-05 09:39:17 +00:00