Andreas Hansson 40d0e6c899 mem: Change accessor function names to match the port interface ...

This patch changes the names of the cache accessor functions to be in
line with those used by the ports. This is done to avoid confusion and
get closer to a one-to-one correspondence between the interface of the
memory object (the cache in this case) and the port itself.

The member function timingAccess has been split into a snoop/non-snoop
part to avoid branching on the isResponse() of the packet.

2013-02-19 05:56:06 -05:00

..

arch

x86: Move APIC clock divider to Python

2013-02-19 05:56:06 -05:00

base

base: Fix a bug in the address interleaving

2013-02-19 05:56:05 -05:00

cpu

x86: Move APIC clock divider to Python

2013-02-19 05:56:06 -05:00

dev

sim: Make clock private and access using clockPeriod()

2013-02-19 05:56:06 -05:00

doc

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

kern

base: Encapsulate the underlying fields in AddrRange

2013-01-07 13:05:38 -05:00

mem

mem: Change accessor function names to match the port interface

2013-02-19 05:56:06 -05:00

proto

scons: Address clang 3.2 compilation error

2013-01-14 10:23:56 -05:00

python

x86: Move APIC clock divider to Python

2013-02-19 05:56:06 -05:00

sim

sim: Make clock private and access using clockPeriod()

2013-02-19 05:56:06 -05:00

unittest

AddrRange: Transition from Range<T> to AddrRange

2012-09-19 06:15:44 -04:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

scons: Remove stale compiler options

2013-01-07 13:05:39 -05:00