40c581be44
Remove uses of six and from __future__ imports as they are no longer needed. Change-Id: I6e2f270557d7343bbad30c8e6d743e363c43715a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39755 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
107 lines
4.2 KiB
Python
107 lines
4.2 KiB
Python
# -*- coding: utf-8 -*-
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# Copyright (c) 2017 Jason Lowe-Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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""" This file creates a barebones system and executes 'hello', a simple Hello
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World application. Adds a simple cache between the CPU and the membus.
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This config file assumes that the x86 ISA was built.
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"""
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# import the m5 (gem5) library created when gem5 is built
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import m5
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# import all of the SimObjects
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from m5.objects import *
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# create the system we are going to simulate
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system = System()
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# Set the clock fequency of the system (and all of its children)
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system.clk_domain = SrcClockDomain()
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system.clk_domain.clock = '1GHz'
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system.clk_domain.voltage_domain = VoltageDomain()
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# Set up the system
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system.mem_mode = 'timing' # Use timing accesses
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system.mem_ranges = [AddrRange('512MB')] # Create an address range
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# Create a simple CPU
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system.cpu = TimingSimpleCPU()
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# Create a memory bus, a coherent crossbar, in this case
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system.membus = SystemXBar()
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# Create a simple cache
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system.cache = SimpleCache(size='1kB')
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# Connect the I and D cache ports of the CPU to the memobj.
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# Since cpu_side is a vector port, each time one of these is connected, it will
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# create a new instance of the CPUSidePort class
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system.cpu.icache_port = system.cache.cpu_side
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system.cpu.dcache_port = system.cache.cpu_side
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# Hook the cache up to the memory bus
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system.cache.mem_side = system.membus.slave
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# create the interrupt controller for the CPU and connect to the membus
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system.cpu.createInterruptController()
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system.cpu.interrupts[0].pio = system.membus.master
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system.cpu.interrupts[0].int_master = system.membus.slave
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system.cpu.interrupts[0].int_slave = system.membus.master
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# Create a DDR3 memory controller and connect it to the membus
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system.mem_ctrl = MemCtrl()
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system.mem_ctrl.dram = DDR3_1600_8x8()
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system.mem_ctrl.dram.range = system.mem_ranges[0]
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system.mem_ctrl.port = system.membus.master
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# Connect the system up to the membus
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system.system_port = system.membus.slave
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# Create a process for a simple "Hello World" application
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process = Process()
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# Set the command
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# grab the specific path to the binary
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thispath = os.path.dirname(os.path.realpath(__file__))
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binpath = os.path.join(thispath, '../../../',
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'tests/test-progs/hello/bin/x86/linux/hello')
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# cmd is a list which begins with the executable (like argv)
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process.cmd = [binpath]
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# Set the cpu to use the process as its workload and create thread contexts
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system.cpu.workload = process
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system.cpu.createThreads()
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system.workload = SEWorkload.init_compatible(binpath)
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# set up the root SimObject and start the simulation
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root = Root(full_system = False, system = system)
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# instantiate all of the objects we've created above
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m5.instantiate()
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print("Beginning simulation!")
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exit_event = m5.simulate()
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print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
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