40c581be44
Remove uses of six and from __future__ imports as they are no longer needed. Change-Id: I6e2f270557d7343bbad30c8e6d743e363c43715a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39755 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
278 lines
12 KiB
Python
278 lines
12 KiB
Python
# Copyright (c) 2013, 2017, 2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import m5.objects
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from common import ObjectList
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from common import HMC
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def create_mem_intf(intf, r, i, nbr_mem_ctrls, intlv_bits, intlv_size,
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xor_low_bit):
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"""
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Helper function for creating a single memoy controller from the given
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options. This function is invoked multiple times in config_mem function
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to create an array of controllers.
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"""
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import math
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intlv_low_bit = int(math.log(intlv_size, 2))
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# Use basic hashing for the channel selection, and preferably use
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# the lower tag bits from the last level cache. As we do not know
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# the details of the caches here, make an educated guess. 4 MByte
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# 4-way associative with 64 byte cache lines is 6 offset bits and
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# 14 index bits.
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if (xor_low_bit):
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xor_high_bit = xor_low_bit + intlv_bits - 1
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else:
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xor_high_bit = 0
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# Create an instance so we can figure out the address
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# mapping and row-buffer size
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interface = intf()
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# Only do this for DRAMs
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if issubclass(intf, m5.objects.DRAMInterface):
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# If the channel bits are appearing after the column
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# bits, we need to add the appropriate number of bits
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# for the row buffer size
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if interface.addr_mapping.value == 'RoRaBaChCo':
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# This computation only really needs to happen
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# once, but as we rely on having an instance we
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# end up having to repeat it for each and every
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# one
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rowbuffer_size = interface.device_rowbuffer_size.value * \
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interface.devices_per_rank.value
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intlv_low_bit = int(math.log(rowbuffer_size, 2))
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# Also adjust interleaving bits for NVM attached as memory
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# Will have separate range defined with unique interleaving
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if issubclass(intf, m5.objects.NVMInterface):
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# If the channel bits are appearing after the low order
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# address bits (buffer bits), we need to add the appropriate
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# number of bits for the buffer size
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if interface.addr_mapping.value == 'RoRaBaChCo':
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# This computation only really needs to happen
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# once, but as we rely on having an instance we
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# end up having to repeat it for each and every
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# one
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buffer_size = interface.per_bank_buffer_size.value
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intlv_low_bit = int(math.log(buffer_size, 2))
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# We got all we need to configure the appropriate address
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# range
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interface.range = m5.objects.AddrRange(r.start, size = r.size(),
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intlvHighBit = \
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intlv_low_bit + intlv_bits - 1,
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xorHighBit = xor_high_bit,
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intlvBits = intlv_bits,
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intlvMatch = i)
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return interface
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def config_mem(options, system):
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"""
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Create the memory controllers based on the options and attach them.
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If requested, we make a multi-channel configuration of the
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selected memory controller class by creating multiple instances of
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the specific class. The individual controllers have their
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parameters set such that the address range is interleaved between
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them.
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"""
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# Mandatory options
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opt_mem_channels = options.mem_channels
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# Semi-optional options
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# Must have either mem_type or nvm_type or both
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opt_mem_type = getattr(options, "mem_type", None)
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opt_nvm_type = getattr(options, "nvm_type", None)
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if not opt_mem_type and not opt_nvm_type:
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fatal("Must have option for either mem-type or nvm-type, or both")
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# Optional options
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opt_tlm_memory = getattr(options, "tlm_memory", None)
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opt_external_memory_system = getattr(options, "external_memory_system",
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None)
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opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
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opt_mem_ranks = getattr(options, "mem_ranks", None)
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opt_nvm_ranks = getattr(options, "nvm_ranks", None)
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opt_hybrid_channel = getattr(options, "hybrid_channel", False)
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opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
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opt_mem_channels_intlv = getattr(options, "mem_channels_intlv", 128)
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opt_xor_low_bit = getattr(options, "xor_low_bit", 0)
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if opt_mem_type == "HMC_2500_1x32":
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HMChost = HMC.config_hmc_host_ctrl(options, system)
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HMC.config_hmc_dev(options, system, HMChost.hmc_host)
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subsystem = system.hmc_dev
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xbar = system.hmc_dev.xbar
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else:
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subsystem = system
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xbar = system.membus
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if opt_tlm_memory:
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system.external_memory = m5.objects.ExternalSlave(
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port_type="tlm_slave",
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port_data=opt_tlm_memory,
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port=system.membus.mem_side_ports,
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addr_ranges=system.mem_ranges)
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system.workload.addr_check = False
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return
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if opt_external_memory_system:
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subsystem.external_memory = m5.objects.ExternalSlave(
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port_type=opt_external_memory_system,
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port_data="init_mem0", port=xbar.master,
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addr_ranges=system.mem_ranges)
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subsystem.workload.addr_check = False
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return
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nbr_mem_ctrls = opt_mem_channels
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import math
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from m5.util import fatal
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intlv_bits = int(math.log(nbr_mem_ctrls, 2))
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if 2 ** intlv_bits != nbr_mem_ctrls:
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fatal("Number of memory channels must be a power of 2")
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if opt_mem_type:
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intf = ObjectList.mem_list.get(opt_mem_type)
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if opt_nvm_type:
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n_intf = ObjectList.mem_list.get(opt_nvm_type)
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nvm_intfs = []
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mem_ctrls = []
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if opt_elastic_trace_en and not issubclass(intf, m5.objects.SimpleMemory):
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fatal("When elastic trace is enabled, configure mem-type as "
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"simple-mem.")
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# The default behaviour is to interleave memory channels on 128
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# byte granularity, or cache line granularity if larger than 128
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# byte. This value is based on the locality seen across a large
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# range of workloads.
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intlv_size = max(opt_mem_channels_intlv, system.cache_line_size.value)
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# For every range (most systems will only have one), create an
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# array of memory interfaces and set their parameters to match
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# their address mapping in the case of a DRAM
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range_iter = 0
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for r in system.mem_ranges:
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# As the loops iterates across ranges, assign them alternatively
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# to DRAM and NVM if both configured, starting with DRAM
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range_iter += 1
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for i in range(nbr_mem_ctrls):
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if opt_mem_type and (not opt_nvm_type or range_iter % 2 != 0):
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# Create the DRAM interface
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dram_intf = create_mem_intf(intf, r, i, nbr_mem_ctrls,
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intlv_bits, intlv_size, opt_xor_low_bit)
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# Set the number of ranks based on the command-line
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# options if it was explicitly set
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if issubclass(intf, m5.objects.DRAMInterface) and \
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opt_mem_ranks:
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dram_intf.ranks_per_channel = opt_mem_ranks
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# Enable low-power DRAM states if option is set
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if issubclass(intf, m5.objects.DRAMInterface):
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dram_intf.enable_dram_powerdown = opt_dram_powerdown
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if opt_elastic_trace_en:
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dram_intf.latency = '1ns'
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print("For elastic trace, over-riding Simple Memory "
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"latency to 1ns.")
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# Create the controller that will drive the interface
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if opt_mem_type == "HMC_2500_1x32":
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# The static latency of the vault controllers is estimated
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# to be smaller than a full DRAM channel controller
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mem_ctrl = m5.objects.MemCtrl(min_writes_per_switch = 8,
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static_backend_latency = '4ns',
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static_frontend_latency = '4ns')
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elif opt_mem_type == "SimpleMemory":
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mem_ctrl = m5.objects.SimpleMemory()
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elif opt_mem_type == "QoSMemSinkInterface":
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mem_ctrl = m5.objects.QoSMemSinkCtrl()
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else:
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mem_ctrl = m5.objects.MemCtrl()
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# Hookup the controller to the interface and add to the list
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if opt_mem_type == "QoSMemSinkInterface":
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mem_ctrl.interface = dram_intf
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elif opt_mem_type != "SimpleMemory":
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mem_ctrl.dram = dram_intf
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mem_ctrls.append(mem_ctrl)
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elif opt_nvm_type and (not opt_mem_type or range_iter % 2 == 0):
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nvm_intf = create_mem_intf(n_intf, r, i, nbr_mem_ctrls,
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intlv_bits, intlv_size)
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# Set the number of ranks based on the command-line
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# options if it was explicitly set
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if issubclass(n_intf, m5.objects.NVMInterface) and \
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opt_nvm_ranks:
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nvm_intf.ranks_per_channel = opt_nvm_ranks
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# Create a controller if not sharing a channel with DRAM
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# in which case the controller has already been created
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if not opt_hybrid_channel:
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mem_ctrl = m5.objects.MemCtrl()
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mem_ctrl.nvm = nvm_intf
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mem_ctrls.append(mem_ctrl)
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else:
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nvm_intfs.append(nvm_intf)
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# hook up NVM interface when channel is shared with DRAM + NVM
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for i in range(len(nvm_intfs)):
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mem_ctrls[i].nvm = nvm_intfs[i];
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# Connect the controller to the xbar port
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for i in range(len(mem_ctrls)):
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if opt_mem_type == "HMC_2500_1x32":
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# Connect the controllers to the membus
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mem_ctrls[i].port = xbar[i/4].mem_side_ports
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# Set memory device size. There is an independent controller
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# for each vault. All vaults are same size.
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mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size
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else:
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# Connect the controllers to the membus
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mem_ctrls[i].port = xbar.mem_side_ports
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subsystem.mem_ctrls = mem_ctrls
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