Giacomo Travaglini 4000480a2f arch-arm: Define ArmFault::invoke32 to match invoke64 ...

Just providing some symmetry to the ArmFault::invoke method

Change-Id: I244e69eee684b9935bea49cf28c6ed99a01192bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50507
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-09-20 09:03:19 +00:00

..

arch

arch-arm: Define ArmFault::invoke32 to match invoke64

2021-09-20 09:03:19 +00:00

base

base: Make the AddrRange::exclude method const.

2021-09-16 20:42:41 +00:00

cpu

cpu-kvm: Reinitialize threads on drainResume

2021-09-19 17:32:59 +00:00

dev

arch-riscv,dev: Explicitly set num CPUs on platform

2021-08-24 23:35:41 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

x86,mem: Replace the x86 StoreCheck flag with READ_MODIFY_WRITE.

2021-09-05 05:29:27 +00:00

kern

misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].

2021-07-29 10:17:51 +00:00

learning_gem5

misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].

2021-07-29 10:17:51 +00:00

mem

mem: Fix for CFI memory

2021-09-20 08:00:53 +00:00

proto

python,scons: Move readCommand and compareVersions into site_scons.

2021-05-10 23:33:22 +00:00

python

sim: Fix fork for multithreaded simulations

2021-09-19 17:32:59 +00:00

sim

sim: Fix fork for multithreaded simulations

2021-09-19 17:32:59 +00:00

systemc

systemc: Stop including mem/port.hh from the systemc headers.

2021-08-28 04:18:12 +00:00

Doxyfile

misc: Replace THE_ISA macro with IS_NULL_ISA.

2021-08-04 21:04:22 +00:00

SConscript

scons: Get rid of a loop which touched all the param ptype attributes.

2021-09-16 20:39:30 +00:00