This generalized Workload SimObject is not geared towards FS or SE simulations, although currently it's only used in FS. This gets rid of the ARM specific highestELIs64 property (from the workload, not the system) and replaces it with a generic getArch. The old globally accessible kernel symtab has been replaced with a symtab accessor which takes a ThreadContext *. The parameter isn't used for anything for now, but in cases where there might be multiple symbol tables to choose from (kernel vs. current user space?) the method will now be able to distinguish which to use. This also makes it possible for the workload to manage its symbol table with whatever policy makes sense for it. That method returns a const SymbolTable * since most of the time the symbol table doesn't need to be modified. In the one case where an external entity needs to modify the table, two pseudo instructions, the table to modify isn't necessarily the one that's currently active. For instance, the pseudo instruction will likely execute in user space, but might be intended to add a symbol to the kernel in case something like a module was loaded. To support that usage, the workload has a generic "insertSymbol" method which will insert the symbol in the table that "makes sense". There is a lot of ambiguity what that means, but it's no less ambiguous than today where we're only saved by the fact that there is generally only one active symbol table to worry about. This change also introduces a KernelWorkload SimObject class which inherits from Workload and adds in kernel related members for cases where the kernel is specified in the config and loaded by gem5 itself. That's the common case, but the base Workload class would be used directly when, for instance, doing a baremetal simulation or if the kernel is loaded by software within the simulation as is the case for SPARC FS. Because a given architecture specific workload class needs to inherit from either Workload or KernelWorkload, this change removes the ability to boot ARM without a kernel. This ability should be restored in the future. To make having or not having a kernel more flexible, the kernel specific members of the KernelWorkload should be factored out into their own object which can then be attached to a workload through a (potentially unused) property rather than inheritance. Change-Id: Idf72615260266d7b4478d20d4035ed5a1e7aa241 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24283 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
164 lines
6.0 KiB
C++
164 lines
6.0 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_THREAD_STATE_HH__
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#define __CPU_O3_THREAD_STATE_HH__
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#include "base/callback.hh"
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#include "base/output.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_state.hh"
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#include "sim/full_system.hh"
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#include "sim/sim_exit.hh"
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class EndQuiesceEvent;
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class Event;
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class FunctionalMemory;
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class FunctionProfile;
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class Process;
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class ProfileNode;
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/**
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* Class that has various thread state, such as the status, the
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* current instruction being processed, whether or not the thread has
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* a trap pending or is being externally updated, the ThreadContext
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* pointer, etc. It also handles anything related to a specific
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* thread's process, such as syscalls and checking valid addresses.
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*/
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template <class Impl>
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struct O3ThreadState : public ThreadState {
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typedef ThreadContext::Status Status;
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typedef typename Impl::O3CPU O3CPU;
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private:
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/** Pointer to the CPU. */
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O3CPU *cpu;
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public:
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PCEventQueue pcEventQueue;
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/**
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* An instruction-based event queue. Used for scheduling events based on
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* number of instructions committed.
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*/
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EventQueue comInstEventQueue;
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/* This variable controls if writes to a thread context should cause a all
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* dynamic/speculative state to be thrown away. Nominally this is the
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* desired behavior because the external thread context write has updated
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* some state that could be used by an inflight instruction, however there
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* are some cases like in a fault/trap handler where this behavior would
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* lead to successive restarts and forward progress couldn't be made. This
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* variable controls if the squashing will occur.
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*/
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bool noSquashFromTC;
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/** Whether or not the thread is currently waiting on a trap, and
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* thus able to be externally updated without squashing.
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*/
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bool trapPending;
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O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
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: ThreadState(_cpu, _thread_num, _process), cpu(_cpu),
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comInstEventQueue("instruction-based event queue"),
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noSquashFromTC(false), trapPending(false), tc(nullptr)
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{
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if (!FullSystem)
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return;
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if (cpu->params()->profile) {
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profile = new FunctionProfile(
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cpu->params()->system->workload->symtab(tc));
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Callback *cb =
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new MakeCallback<O3ThreadState,
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&O3ThreadState::dumpFuncProfile>(this);
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registerExitCallback(cb);
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}
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// let's fill with a dummy node for now so we don't get a segfault
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// on the first cycle when there's no node available.
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static ProfileNode dummyNode;
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profileNode = &dummyNode;
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profilePC = 3;
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}
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void serialize(CheckpointOut &cp) const override
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{
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ThreadState::serialize(cp);
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// Use the ThreadContext serialization helper to serialize the
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// TC.
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::serialize(*tc, cp);
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}
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void unserialize(CheckpointIn &cp) override
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{
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// Prevent squashing - we don't have any instructions in
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// flight that we need to squash since we just instantiated a
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// clean system.
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noSquashFromTC = true;
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ThreadState::unserialize(cp);
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// Use the ThreadContext serialization helper to unserialize
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// the TC.
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::unserialize(*tc, cp);
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noSquashFromTC = false;
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}
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/** Pointer to the ThreadContext of this thread. */
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ThreadContext *tc;
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/** Returns a pointer to the TC of this thread. */
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ThreadContext *getTC() { return tc; }
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/** Handles the syscall. */
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void syscall(Fault *fault)
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{
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process->syscall(tc, fault);
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}
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void dumpFuncProfile()
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{
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OutputStream *os(
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simout.create(csprintf("profile.%s.dat", cpu->name())));
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profile->dump(tc, *os->stream());
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simout.close(os);
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}
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};
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#endif // __CPU_O3_THREAD_STATE_HH__
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