8acf49b6fa
The new implementation matches the table in the ARM Architecture Reference Manual (version DDI 0487J.a, section D1.3.6, table R_SXLWJ) It takes into consideration features like FEAT_SEL2 (scr.eel2 bit) and FEAT_VHE (hcr.e2h bit) which affect the masking of interrupts under certain circumstances Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: I07ebd8d859651475bd32fd201eea0f4e64a7dd5f
289 lines
10 KiB
C++
289 lines
10 KiB
C++
/*
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* Copyright (c) 2009, 2012-2013, 2016, 2019, 2023 Arm Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/arm/interrupts.hh"
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#include "arch/arm/system.hh"
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namespace gem5
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{
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bool
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ArmISA::Interrupts::takeInt32(InterruptTypes int_type) const
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{
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InterruptMask mask;
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);;
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HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
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ExceptionLevel el = currEL(tc);
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bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
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bool is_secure = isSecure(tc);
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switch(int_type) {
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case INT_FIQ:
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cpsr_mask_bit = cpsr.f;
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scr_routing_bit = scr.fiq;
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scr_fwaw_bit = scr.fw;
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hcr_mask_override_bit = hcr.fmo;
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break;
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case INT_IRQ:
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cpsr_mask_bit = cpsr.i;
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scr_routing_bit = scr.irq;
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scr_fwaw_bit = 1;
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hcr_mask_override_bit = hcr.imo;
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break;
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case INT_ABT:
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cpsr_mask_bit = cpsr.a;
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scr_routing_bit = scr.ea;
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scr_fwaw_bit = scr.aw;
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hcr_mask_override_bit = hcr.amo;
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break;
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default:
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panic("Unhandled interrupt type!");
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}
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if (hcr.tge)
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hcr_mask_override_bit = 1;
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if (!scr_routing_bit) {
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// SCR IRQ == 0
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if (!hcr_mask_override_bit)
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mask = INT_MASK_M;
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else {
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if (!is_secure && (el == EL0 || el == EL1))
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mask = INT_MASK_T;
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else
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mask = INT_MASK_M;
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}
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} else {
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// SCR IRQ == 1
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if ((!is_secure) &&
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(hcr_mask_override_bit ||
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(!scr_fwaw_bit && !hcr_mask_override_bit)))
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mask = INT_MASK_T;
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else
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mask = INT_MASK_M;
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}
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return ((mask == INT_MASK_T) ||
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((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
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(mask != INT_MASK_P);
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}
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bool
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ArmISA::Interrupts::takeInt64(InterruptTypes int_type) const
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{
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InterruptMask mask;
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);;
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HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
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ExceptionLevel el = currEL(tc);
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bool cpsr_mask_bit, scr_routing_bit, hcr_mask_override_bit;
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bool is_secure = isSecureBelowEL3(tc);
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switch(int_type) {
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case INT_FIQ:
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cpsr_mask_bit = cpsr.f;
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scr_routing_bit = scr.fiq;
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hcr_mask_override_bit = hcr.fmo;
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break;
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case INT_IRQ:
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cpsr_mask_bit = cpsr.i;
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scr_routing_bit = scr.irq;
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hcr_mask_override_bit = hcr.imo;
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break;
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case INT_ABT:
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cpsr_mask_bit = cpsr.a;
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scr_routing_bit = scr.ea;
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hcr_mask_override_bit = hcr.amo;
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break;
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default:
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panic("Unhandled interrupt type!");
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}
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if (is_secure) {
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if (!scr.eel2) {
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if (!scr_routing_bit) {
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// NS=0,EEL2=0,EAI/IRQ/FIQ=0
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if (el == EL3)
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mask = INT_MASK_P;
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else
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mask = INT_MASK_M;
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} else {
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// NS=0,EEL2=0,EAI/IRQ/FIQ=1
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if (el == EL3)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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}
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} else {
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if (!scr_routing_bit) {
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if (!hcr.tge) {
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if (!hcr_mask_override_bit) {
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// NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=0,AMO/IMO/FMO=0
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if (el == EL3 || el == EL2)
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mask = INT_MASK_P;
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else
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mask = INT_MASK_M;
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} else {
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// NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=0,AMO/IMO/FMO=1
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if (el == EL3)
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mask = INT_MASK_P;
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else if (el == EL2)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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}
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} else {
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if (!hcr.e2h) {
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// NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=1,E2H=0
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if (el == EL3)
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mask = INT_MASK_P;
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else if (el == EL2)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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} else {
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// NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=1,E2H=1
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if (el == EL3)
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mask = INT_MASK_P;
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else
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mask = INT_MASK_M;
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}
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}
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} else {
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if (!hcr.tge) {
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// NS=0,EEL2=1,EAI/IRQ/FIQ=1,TGE=0
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if (el == EL3)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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} else {
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// NS=0,EEL2=1,EAI/IRQ/FIQ=1,TGE=1
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if (el == EL3)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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}
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}
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}
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} else {
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if (!scr_routing_bit) {
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if (!scr.rw) {
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if (!hcr.tge) {
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if (!hcr_mask_override_bit) {
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// NS=1,EAI/IRQ/FIQ=0,RW=0,TGE=0,AMO/IMO?/FMO=0
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if (el == EL3)
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mask = INT_MASK_P;
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else
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mask = INT_MASK_M;
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} else {
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// NS=1,EAI/IRQ/FIQ=0,RW=0,TGE=0,AMO/IMO?/FMO=1
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if (el == EL3)
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mask = INT_MASK_P;
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else if (el == EL2)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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}
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} else {
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// NS=1,EAI/IRQ/FIQ=0,RW=0,TGE=1
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if (el == EL3)
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mask = INT_MASK_P;
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else if (el == EL2)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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}
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} else {
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if (!hcr.tge) {
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if (!hcr_mask_override_bit) {
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// NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=0,AMO/IMO/FMO=0
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if (el == EL3 || el == EL2)
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mask = INT_MASK_P;
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else
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mask = INT_MASK_M;
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} else {
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// NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=0,AMO/IMO/FMO=1
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if (el == EL3)
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mask = INT_MASK_P;
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else if (el == EL2)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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}
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} else {
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if (!hcr.e2h) {
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// NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=1,E2H=0
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if (el == EL3)
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mask = INT_MASK_P;
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else if (el == EL2)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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} else {
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// NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=1,E2H=1
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if (el == EL3)
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mask = INT_MASK_P;
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else
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mask = INT_MASK_M;
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}
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}
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}
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} else {
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if (el == EL3)
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mask = INT_MASK_M;
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else
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mask = INT_MASK_T;
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}
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}
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return ((mask == INT_MASK_T) ||
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((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
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(mask != INT_MASK_P);
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}
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bool
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ArmISA::Interrupts::takeInt(InterruptTypes int_type) const
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{
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// Table G1-17~19 of ARM V8 ARM
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return ArmSystem::highestELIs64(tc) ? takeInt64(int_type) :
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takeInt32(int_type);
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}
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} // namespace gem5
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