e923c07ab0
This is addressing an issue raised in the mailing list [1]
where setting up a PCI mem bar for an ethernet device
resulted into an overlap of memory ranges:
fatal: system.iobus has two ports responding within range
[0x80000000:0x80020000]:
system.realview.ethernet.pio
system.iobridge.cpu_side_port
The reason for this is the following:
The PCI mem range in the DTB is using 0x40000000 (3rd word) as a
starting address in the PCI domain, which is linked to 0x40000000 in the
host domain.
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
However the current mapping scheme works with simple fixed translation
So address 0x40000000 in the PCI domain will be mapped to 0x40000000 +
0x40000000 = 0x80000000, which is where DRAM starts
This is aligning with DTB autogeneration, which is setting up a
PCI mem range starting at PCI address = 0 [2]
[1]: https://www.mail-archive.com/gem5-users@gem5.org/msg18941.html
[2]: https://github.com/gem5/gem5/blob/v20.1.0.0/src/dev/arm/RealView.py#L161
Change-Id: I4538511453cfd5143fb4613a080780dc86b2244c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39915
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
184 lines
5.1 KiB
Plaintext
184 lines
5.1 KiB
Plaintext
/*
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* Copyright (c) 2015-2017 ARM Limited
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/ {
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arm,hbi = <0x0>;
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arm,vexpress,site = <0xf>;
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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gic: interrupt-controller@2c001000 {
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compatible = "gem5,gic", "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x1000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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clocks = <&osc_sys>;
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clock-names="apb_pclk";
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};
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pci {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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#address-cells = <0x3>;
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#size-cells = <0x2>;
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#interrupt-cells = <0x1>;
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reg = <0x0 0x30000000 0x0 0x10000000>;
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ranges = <0x01000000 0x0 0x0 0x0 0x2f000000 0x0 0x00010000>,
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<0x02000000 0x0 0x0 0x0 0x40000000 0x0 0x40000000>;
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interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>,
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<0x000800 0x0 0x0 0 &gic 0 69 1>,
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<0x001000 0x0 0x0 0 &gic 0 70 1>,
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<0x001800 0x0 0x0 0 &gic 0 71 1>;
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interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
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dma-coherent;
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};
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kmi@1c060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c060000 0x0 0x1000>;
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interrupts = <0 12 4>;
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clocks = <&v2m_clk24mhz>, <&osc_smb>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c070000 0x0 0x1000>;
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interrupts = <0 13 4>;
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clocks = <&v2m_clk24mhz>, <&osc_smb>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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uart0: uart@1c090000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x1c090000 0x0 0x1000>;
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interrupts = <0 5 4>;
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clocks = <&osc_peripheral>, <&osc_smb>;
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clock-names = "uartclk", "apb_pclk";
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};
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rtc@1c170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x0 0x1c170000 0x0 0x1000>;
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interrupts = <0 4 4>;
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clocks = <&osc_smb>;
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clock-names = "apb_pclk";
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_sysreg: sysreg@1c010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0 0x1c010000 0x0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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vio@1c130000 {
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compatible = "virtio,mmio";
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reg = <0 0x1c130000 0x0 0x1000>;
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interrupts = <0 42 4>;
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};
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vio@1c140000 {
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compatible = "virtio,mmio";
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reg = <0 0x1c140000 0x0 0x1000>;
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interrupts = <0 43 4>;
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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osc_pxl: osc@5 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 5>;
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freq-range = <23750000 1000000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk5";
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};
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osc_smb: osc@6 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 6>;
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freq-range = <20000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk6";
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};
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osc_sys: osc@7 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 7>;
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freq-range = <20000000 60000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk7";
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};
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};
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mcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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arm,vexpress,site = <0>;
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osc_peripheral: osc@2 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 2>;
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freq-range = <24000000 24000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk2";
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};
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};
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};
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