Ron Dreslinski 3c7e0ec752 Fix bus in FS mode. ...

src/mem/bus.cc:
    Add debugging statement
src/mem/bus.hh:
    Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
    Rework timing port to retry properly

--HG--
extra : convert_revision : fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2

2006-10-11 19:25:48 -04:00

..

arch

Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)

2006-10-08 10:53:24 -07:00

base

Debugging info

2006-10-10 22:50:36 -04:00

cpu

More cache fixes. Atomic coherence now works as well.

2006-10-11 18:28:33 -04:00

dev

post checkpoint restoration the bus ranges need to be re-initialized for ALL pci devs, not just ide.

2006-10-08 23:18:19 -04:00

doxygen

Fix up doxygen.

2006-08-14 19:25:07 -04:00

kern

Allocate new thread stacks and shared mem region via Process page table

2006-10-08 04:29:40 -04:00

mem

Fix bus in FS mode.

2006-10-11 19:25:48 -04:00

python

More cache fixes. Atomic coherence now works as well.

2006-10-11 18:28:33 -04:00

sim

Merge zizzer:/bk/newmem

2006-10-06 21:46:04 -04:00

unittest

Merge iceaxe.:/Volumes/work/research/m5/head

2006-06-11 22:01:34 -04:00

Doxyfile

Fix up doxygen.

2006-08-14 19:25:07 -04:00

SConscript

Two minor fixes.

2006-10-10 01:49:46 -04:00