38925ff621
In order to see all registers independent of the current CPU mode, the ARM architecture model uses the magic MISCREG_CPSR_MODE register to change the register mappings without actually updating the CPU mode. This hack is no longer needed since the thread context now provides a flat interface to the register file. This patch replaces the CPSR_MODE hack with the flat register interface.
672 lines
23 KiB
C++
672 lines
23 KiB
C++
/*
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* Copyright (c) 2010-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#include "arch/arm/isa.hh"
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#include "arch/arm/system.hh"
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#include "cpu/checker/cpu.hh"
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#include "debug/Arm.hh"
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#include "debug/MiscRegs.hh"
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#include "params/ArmISA.hh"
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#include "sim/faults.hh"
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#include "sim/stat_control.hh"
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#include "sim/system.hh"
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namespace ArmISA
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{
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ISA::ISA(Params *p)
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: SimObject(p)
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{
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SCTLR sctlr;
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sctlr = 0;
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miscRegs[MISCREG_SCTLR_RST] = sctlr;
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clear();
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}
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const ArmISAParams *
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ISA::params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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void
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ISA::clear()
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{
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const Params *p(params());
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SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
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memset(miscRegs, 0, sizeof(miscRegs));
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CPSR cpsr = 0;
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cpsr.mode = MODE_USER;
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miscRegs[MISCREG_CPSR] = cpsr;
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updateRegMap(cpsr);
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SCTLR sctlr = 0;
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sctlr.te = (bool)sctlr_rst.te;
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sctlr.nmfi = (bool)sctlr_rst.nmfi;
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sctlr.v = (bool)sctlr_rst.v;
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sctlr.u = 1;
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sctlr.xp = 1;
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sctlr.rao2 = 1;
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sctlr.rao3 = 1;
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sctlr.rao4 = 1;
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miscRegs[MISCREG_SCTLR] = sctlr;
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miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
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/* Start with an event in the mailbox */
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miscRegs[MISCREG_SEV_MAILBOX] = 1;
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// Separate Instruction and Data TLBs.
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miscRegs[MISCREG_TLBTR] = 1;
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MVFR0 mvfr0 = 0;
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mvfr0.advSimdRegisters = 2;
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mvfr0.singlePrecision = 2;
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mvfr0.doublePrecision = 2;
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mvfr0.vfpExceptionTrapping = 0;
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mvfr0.divide = 1;
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mvfr0.squareRoot = 1;
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mvfr0.shortVectors = 1;
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mvfr0.roundingModes = 1;
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miscRegs[MISCREG_MVFR0] = mvfr0;
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MVFR1 mvfr1 = 0;
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mvfr1.flushToZero = 1;
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mvfr1.defaultNaN = 1;
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mvfr1.advSimdLoadStore = 1;
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mvfr1.advSimdInteger = 1;
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mvfr1.advSimdSinglePrecision = 1;
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mvfr1.advSimdHalfPrecision = 1;
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mvfr1.vfpHalfPrecision = 1;
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miscRegs[MISCREG_MVFR1] = mvfr1;
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// Reset values of PRRR and NMRR are implementation dependent
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miscRegs[MISCREG_PRRR] =
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(1 << 19) | // 19
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(0 << 18) | // 18
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(0 << 17) | // 17
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(1 << 16) | // 16
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(2 << 14) | // 15:14
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(0 << 12) | // 13:12
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(2 << 10) | // 11:10
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(2 << 8) | // 9:8
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(2 << 6) | // 7:6
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(2 << 4) | // 5:4
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(1 << 2) | // 3:2
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0; // 1:0
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miscRegs[MISCREG_NMRR] =
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(1 << 30) | // 31:30
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(0 << 26) | // 27:26
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(0 << 24) | // 25:24
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(3 << 22) | // 23:22
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(2 << 20) | // 21:20
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(0 << 18) | // 19:18
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(0 << 16) | // 17:16
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(1 << 14) | // 15:14
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(0 << 12) | // 13:12
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(2 << 10) | // 11:10
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(0 << 8) | // 9:8
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(3 << 6) | // 7:6
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(2 << 4) | // 5:4
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(0 << 2) | // 3:2
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0; // 1:0
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miscRegs[MISCREG_CPACR] = 0;
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// Initialize configurable default values
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miscRegs[MISCREG_MIDR] = p->midr;
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miscRegs[MISCREG_ID_PFR0] = p->id_pfr0;
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miscRegs[MISCREG_ID_PFR1] = p->id_pfr1;
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miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
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miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
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miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
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miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
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miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
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miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
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miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
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miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
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miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
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miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
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miscRegs[MISCREG_FPSID] = p->fpsid;
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//XXX We need to initialize the rest of the state.
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}
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MiscReg
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ISA::readMiscRegNoEffect(int misc_reg)
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{
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assert(misc_reg < NumMiscRegs);
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int flat_idx;
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if (misc_reg == MISCREG_SPSR)
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flat_idx = flattenMiscIndex(misc_reg);
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else
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flat_idx = misc_reg;
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MiscReg val = miscRegs[flat_idx];
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DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
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misc_reg, flat_idx, val);
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return val;
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}
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MiscReg
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ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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{
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ArmSystem *arm_sys;
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if (misc_reg == MISCREG_CPSR) {
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CPSR cpsr = miscRegs[misc_reg];
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PCState pc = tc->pcState();
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cpsr.j = pc.jazelle() ? 1 : 0;
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cpsr.t = pc.thumb() ? 1 : 0;
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return cpsr;
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}
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if (misc_reg >= MISCREG_CP15_UNIMP_START)
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panic("Unimplemented CP15 register %s read.\n",
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miscRegName[misc_reg]);
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switch (misc_reg) {
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case MISCREG_MPIDR:
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arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr());
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assert(arm_sys);
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if (arm_sys->multiProc) {
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return 0x80000000 | // multiprocessor extensions available
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tc->cpuId();
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} else {
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return 0x80000000 | // multiprocessor extensions available
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0x40000000 | // in up system
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tc->cpuId();
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}
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break;
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case MISCREG_CLIDR:
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warn_once("The clidr register always reports 0 caches.\n");
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warn_once("clidr LoUIS field of 0b001 to match current "
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"ARM implementations.\n");
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return 0x00200000;
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case MISCREG_CCSIDR:
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warn_once("The ccsidr register isn't implemented and "
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"always reads as 0.\n");
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break;
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case MISCREG_CTR:
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{
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//all caches have the same line size in gem5
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//4 byte words in ARM
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unsigned lineSizeWords =
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tc->getCpuPtr()->getInstPort().peerBlockSize() / 4;
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unsigned log2LineSizeWords = 0;
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while (lineSizeWords >>= 1) {
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++log2LineSizeWords;
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}
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CTR ctr = 0;
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//log2 of minimun i-cache line size (words)
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ctr.iCacheLineSize = log2LineSizeWords;
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//b11 - gem5 uses pipt
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ctr.l1IndexPolicy = 0x3;
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//log2 of minimum d-cache line size (words)
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ctr.dCacheLineSize = log2LineSizeWords;
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//log2 of max reservation size (words)
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ctr.erg = log2LineSizeWords;
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//log2 of max writeback size (words)
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ctr.cwg = log2LineSizeWords;
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//b100 - gem5 format is ARMv7
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ctr.format = 0x4;
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return ctr;
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}
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case MISCREG_ACTLR:
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warn("Not doing anything for miscreg ACTLR\n");
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break;
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case MISCREG_PMCR:
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case MISCREG_PMCCNTR:
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case MISCREG_PMSELR:
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warn("Not doing anything for read to miscreg %s\n",
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miscRegName[misc_reg]);
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break;
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case MISCREG_CPSR_Q:
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panic("shouldn't be reading this register seperately\n");
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case MISCREG_FPSCR_QC:
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return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
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case MISCREG_FPSCR_EXC:
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return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
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case MISCREG_L2CTLR:
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{
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// mostly unimplemented, just set NumCPUs field from sim and return
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L2CTLR l2ctlr = 0;
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// b00:1CPU to b11:4CPUs
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l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
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return l2ctlr;
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}
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case MISCREG_DBGDIDR:
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/* For now just implement the version number.
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* Return 0 as we don't support debug architecture yet.
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*/
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return 0;
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case MISCREG_DBGDSCR_INT:
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return 0;
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}
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return readMiscRegNoEffect(misc_reg);
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}
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void
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ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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assert(misc_reg < NumMiscRegs);
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int flat_idx;
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if (misc_reg == MISCREG_SPSR)
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flat_idx = flattenMiscIndex(misc_reg);
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else
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flat_idx = misc_reg;
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miscRegs[flat_idx] = val;
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DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
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flat_idx, val);
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}
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void
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ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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{
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MiscReg newVal = val;
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int x;
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System *sys;
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ThreadContext *oc;
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if (misc_reg == MISCREG_CPSR) {
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updateRegMap(val);
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CPSR old_cpsr = miscRegs[MISCREG_CPSR];
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int old_mode = old_cpsr.mode;
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CPSR cpsr = val;
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if (old_mode != cpsr.mode) {
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tc->getITBPtr()->invalidateMiscReg();
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tc->getDTBPtr()->invalidateMiscReg();
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}
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DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
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miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
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PCState pc = tc->pcState();
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pc.nextThumb(cpsr.t);
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pc.nextJazelle(cpsr.j);
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// Follow slightly different semantics if a CheckerCPU object
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// is connected
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CheckerCPU *checker = tc->getCheckerCpuPtr();
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if (checker) {
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tc->pcStateNoRecord(pc);
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} else {
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tc->pcState(pc);
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}
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} else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s wrote with %#x.\n",
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miscRegName[misc_reg], val);
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} else {
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switch (misc_reg) {
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case MISCREG_CPACR:
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{
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const uint32_t ones = (uint32_t)(-1);
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CPACR cpacrMask = 0;
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// Only cp10, cp11, and ase are implemented, nothing else should
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// be writable
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cpacrMask.cp10 = ones;
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cpacrMask.cp11 = ones;
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cpacrMask.asedis = ones;
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newVal &= cpacrMask;
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DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
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miscRegName[misc_reg], newVal);
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}
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break;
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case MISCREG_CSSELR:
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warn_once("The csselr register isn't implemented.\n");
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return;
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case MISCREG_FPSCR:
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{
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const uint32_t ones = (uint32_t)(-1);
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FPSCR fpscrMask = 0;
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fpscrMask.ioc = ones;
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fpscrMask.dzc = ones;
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fpscrMask.ofc = ones;
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fpscrMask.ufc = ones;
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fpscrMask.ixc = ones;
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fpscrMask.idc = ones;
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fpscrMask.len = ones;
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fpscrMask.stride = ones;
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fpscrMask.rMode = ones;
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fpscrMask.fz = ones;
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fpscrMask.dn = ones;
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fpscrMask.ahp = ones;
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fpscrMask.qc = ones;
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fpscrMask.v = ones;
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fpscrMask.c = ones;
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fpscrMask.z = ones;
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fpscrMask.n = ones;
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newVal = (newVal & (uint32_t)fpscrMask) |
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(miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
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tc->getDecoderPtr()->setContext(newVal);
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}
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break;
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case MISCREG_CPSR_Q:
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{
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assert(!(newVal & ~CpsrMaskQ));
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newVal = miscRegs[MISCREG_CPSR] | newVal;
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misc_reg = MISCREG_CPSR;
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}
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break;
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case MISCREG_FPSCR_QC:
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{
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newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
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misc_reg = MISCREG_FPSCR;
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}
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break;
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case MISCREG_FPSCR_EXC:
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{
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newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
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misc_reg = MISCREG_FPSCR;
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}
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break;
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case MISCREG_FPEXC:
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{
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// vfpv3 architecture, section B.6.1 of DDI04068
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// bit 29 - valid only if fpexc[31] is 0
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const uint32_t fpexcMask = 0x60000000;
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newVal = (newVal & fpexcMask) |
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(miscRegs[MISCREG_FPEXC] & ~fpexcMask);
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}
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break;
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case MISCREG_SCTLR:
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{
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DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
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SCTLR sctlr = miscRegs[MISCREG_SCTLR];
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SCTLR new_sctlr = newVal;
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new_sctlr.nmfi = (bool)sctlr.nmfi;
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miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
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tc->getITBPtr()->invalidateMiscReg();
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tc->getDTBPtr()->invalidateMiscReg();
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// Check if all CPUs are booted with caches enabled
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// so we can stop enforcing coherency of some kernel
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// structures manually.
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sys = tc->getSystemPtr();
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for (x = 0; x < sys->numContexts(); x++) {
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oc = sys->getThreadContext(x);
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SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
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if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
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return;
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}
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for (x = 0; x < sys->numContexts(); x++) {
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oc = sys->getThreadContext(x);
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oc->getDTBPtr()->allCpusCaching();
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oc->getITBPtr()->allCpusCaching();
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// If CheckerCPU is connected, need to notify it.
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CheckerCPU *checker = oc->getCheckerCpuPtr();
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if (checker) {
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checker->getDTBPtr()->allCpusCaching();
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checker->getITBPtr()->allCpusCaching();
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}
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}
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return;
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}
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case MISCREG_MIDR:
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case MISCREG_ID_PFR0:
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case MISCREG_ID_PFR1:
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case MISCREG_ID_MMFR0:
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case MISCREG_ID_MMFR1:
|
|
case MISCREG_ID_MMFR2:
|
|
case MISCREG_ID_MMFR3:
|
|
case MISCREG_ID_ISAR0:
|
|
case MISCREG_ID_ISAR1:
|
|
case MISCREG_ID_ISAR2:
|
|
case MISCREG_ID_ISAR3:
|
|
case MISCREG_ID_ISAR4:
|
|
case MISCREG_ID_ISAR5:
|
|
|
|
case MISCREG_MPIDR:
|
|
case MISCREG_FPSID:
|
|
case MISCREG_TLBTR:
|
|
case MISCREG_MVFR0:
|
|
case MISCREG_MVFR1:
|
|
// ID registers are constants.
|
|
return;
|
|
|
|
case MISCREG_TLBIALLIS:
|
|
case MISCREG_TLBIALL:
|
|
sys = tc->getSystemPtr();
|
|
for (x = 0; x < sys->numContexts(); x++) {
|
|
oc = sys->getThreadContext(x);
|
|
assert(oc->getITBPtr() && oc->getDTBPtr());
|
|
oc->getITBPtr()->flushAll();
|
|
oc->getDTBPtr()->flushAll();
|
|
|
|
// If CheckerCPU is connected, need to notify it of a flush
|
|
CheckerCPU *checker = oc->getCheckerCpuPtr();
|
|
if (checker) {
|
|
checker->getITBPtr()->flushAll();
|
|
checker->getDTBPtr()->flushAll();
|
|
}
|
|
}
|
|
return;
|
|
case MISCREG_ITLBIALL:
|
|
tc->getITBPtr()->flushAll();
|
|
return;
|
|
case MISCREG_DTLBIALL:
|
|
tc->getDTBPtr()->flushAll();
|
|
return;
|
|
case MISCREG_TLBIMVAIS:
|
|
case MISCREG_TLBIMVA:
|
|
sys = tc->getSystemPtr();
|
|
for (x = 0; x < sys->numContexts(); x++) {
|
|
oc = sys->getThreadContext(x);
|
|
assert(oc->getITBPtr() && oc->getDTBPtr());
|
|
oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
|
|
CheckerCPU *checker = oc->getCheckerCpuPtr();
|
|
if (checker) {
|
|
checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
}
|
|
}
|
|
return;
|
|
case MISCREG_TLBIASIDIS:
|
|
case MISCREG_TLBIASID:
|
|
sys = tc->getSystemPtr();
|
|
for (x = 0; x < sys->numContexts(); x++) {
|
|
oc = sys->getThreadContext(x);
|
|
assert(oc->getITBPtr() && oc->getDTBPtr());
|
|
oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
|
|
oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
|
|
CheckerCPU *checker = oc->getCheckerCpuPtr();
|
|
if (checker) {
|
|
checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
|
|
checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
|
|
}
|
|
}
|
|
return;
|
|
case MISCREG_TLBIMVAAIS:
|
|
case MISCREG_TLBIMVAA:
|
|
sys = tc->getSystemPtr();
|
|
for (x = 0; x < sys->numContexts(); x++) {
|
|
oc = sys->getThreadContext(x);
|
|
assert(oc->getITBPtr() && oc->getDTBPtr());
|
|
oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
|
|
oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
|
|
|
|
CheckerCPU *checker = oc->getCheckerCpuPtr();
|
|
if (checker) {
|
|
checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
|
|
checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
|
|
}
|
|
}
|
|
return;
|
|
case MISCREG_ITLBIMVA:
|
|
tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
return;
|
|
case MISCREG_DTLBIMVA:
|
|
tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
return;
|
|
case MISCREG_ITLBIASID:
|
|
tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
|
|
return;
|
|
case MISCREG_DTLBIASID:
|
|
tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
|
|
return;
|
|
case MISCREG_ACTLR:
|
|
warn("Not doing anything for write of miscreg ACTLR\n");
|
|
break;
|
|
case MISCREG_PMCR:
|
|
{
|
|
// Performance counters not implemented. Instead, interpret
|
|
// a reset command to this register to reset the simulator
|
|
// statistics.
|
|
// PMCR_E | PMCR_P | PMCR_C
|
|
const int ResetAndEnableCounters = 0x7;
|
|
if (newVal == ResetAndEnableCounters) {
|
|
inform("Resetting all simobject stats\n");
|
|
Stats::schedStatEvent(false, true);
|
|
break;
|
|
}
|
|
}
|
|
case MISCREG_PMCCNTR:
|
|
case MISCREG_PMSELR:
|
|
warn("Not doing anything for write to miscreg %s\n",
|
|
miscRegName[misc_reg]);
|
|
break;
|
|
case MISCREG_V2PCWPR:
|
|
case MISCREG_V2PCWPW:
|
|
case MISCREG_V2PCWUR:
|
|
case MISCREG_V2PCWUW:
|
|
case MISCREG_V2POWPR:
|
|
case MISCREG_V2POWPW:
|
|
case MISCREG_V2POWUR:
|
|
case MISCREG_V2POWUW:
|
|
{
|
|
RequestPtr req = new Request;
|
|
unsigned flags;
|
|
BaseTLB::Mode mode;
|
|
Fault fault;
|
|
switch(misc_reg) {
|
|
case MISCREG_V2PCWPR:
|
|
flags = TLB::MustBeOne;
|
|
mode = BaseTLB::Read;
|
|
break;
|
|
case MISCREG_V2PCWPW:
|
|
flags = TLB::MustBeOne;
|
|
mode = BaseTLB::Write;
|
|
break;
|
|
case MISCREG_V2PCWUR:
|
|
flags = TLB::MustBeOne | TLB::UserMode;
|
|
mode = BaseTLB::Read;
|
|
break;
|
|
case MISCREG_V2PCWUW:
|
|
flags = TLB::MustBeOne | TLB::UserMode;
|
|
mode = BaseTLB::Write;
|
|
break;
|
|
default:
|
|
panic("Security Extensions not implemented!");
|
|
}
|
|
warn("Translating via MISCREG in atomic mode! Fix Me!\n");
|
|
req->setVirt(0, val, 1, flags, tc->pcState().pc(),
|
|
Request::funcMasterId);
|
|
fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
|
|
if (fault == NoFault) {
|
|
miscRegs[MISCREG_PAR] =
|
|
(req->getPaddr() & 0xfffff000) |
|
|
(tc->getDTBPtr()->getAttr() );
|
|
DPRINTF(MiscRegs,
|
|
"MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
|
|
val, miscRegs[MISCREG_PAR]);
|
|
}
|
|
else {
|
|
// Set fault bit and FSR
|
|
FSR fsr = miscRegs[MISCREG_DFSR];
|
|
miscRegs[MISCREG_PAR] =
|
|
(fsr.ext << 6) |
|
|
(fsr.fsHigh << 5) |
|
|
(fsr.fsLow << 1) |
|
|
0x1; // F bit
|
|
}
|
|
return;
|
|
}
|
|
case MISCREG_CONTEXTIDR:
|
|
case MISCREG_PRRR:
|
|
case MISCREG_NMRR:
|
|
case MISCREG_DACR:
|
|
tc->getITBPtr()->invalidateMiscReg();
|
|
tc->getDTBPtr()->invalidateMiscReg();
|
|
break;
|
|
case MISCREG_L2CTLR:
|
|
warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
|
|
miscRegName[misc_reg], uint32_t(val));
|
|
}
|
|
}
|
|
setMiscRegNoEffect(misc_reg, newVal);
|
|
}
|
|
|
|
}
|
|
|
|
ArmISA::ISA *
|
|
ArmISAParams::create()
|
|
{
|
|
return new ArmISA::ISA(this);
|
|
}
|